Forum: FPGA, VHDL & Verilog Someone please help me about it (!) 16x1 mux More actuals found than formals in port map

von Yusuf Y. (Company: turkey) (orkcan)

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This is my homework we are building 16x1 mux  with using 2x1 mux. my 
2x1mux and 4x1mux modules are correctly working but in 16x1 mux i got  " 
More actuals found than formals in port map" error in port map 
codes.(for n0,n1,n2,n3,n4) If somebody could help me I'll be 

thank you in advance.

entity mux16x1 is
    Port ( g : in  STD_LOGIC_VECTOR (7 downto 0);
        h : in  STD_LOGIC_VECTOR (7 downto 0);
           sele : in  STD_LOGIC_VECTOR (1 downto 0);
           zout : out  STD_LOGIC);
end mux16x1;

architecture Behavioral of mux16x1 is

signal k1,k2,k3,k4: std_logic ;
component mux4x1 is
  Port ( b : in  STD_LOGIC_VECTOR (1 downto 0);
        a : in  STD_LOGIC_VECTOR (1 downto 0);
           sel : in  STD_LOGIC_VECTOR (1 downto 0);
           z : out  STD_LOGIC);
end component;

  n0:mux4x1 port map(g(0),g(1),h(0),h(1),sele(0),k1);
  n1:mux4x1 port map(g(2),g(3),h(2),h(3),sele(0),k2);
  n2:mux4x1 port map(g(4),g(5),h(4),h(5),sele(0),k3);
  n3:mux4x1 port map(g(6),g(7),h(6),h(7),sele(0),k4);
  n4:mux4x1 port map(k1,k2,k3,k4,sele(1),zout);

end Behavioral;

: Edited by User
von Lothar M. (lkmiller) (Moderator)

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Your mix port has 4 elements, in the port map you try to connect 7 
ports. If you want to connect single bits you must use explicit signal 


Then you will see, that one signal is missing in the map: you try to 
connect 6 signals while the port itself has 7 signals...


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