VHDL fill rest of the vector in assignment
Guest
#3543565
Hello, I'd like to assign a value to an std_logic_vector, and fill the rest of the vector with zeros. The length of the vector is defined with a generic or a constant. So it would be like this (but this does not work): signal my_signal : std_logic_vector(CONST_WIDTH downto 0); my_signal <= (others => '0') & x"2"; It could be done with a for generate statement, but are there any shorter and nicer solutions? Václav wrote: > but are there any shorter and nicer solutions? Have a look for the resize() function in the numeric_std lib. But keep in mind: this function only works for signed and unsigned vectors, not for a std_logic_vector.
Guest
#3543686
Oh this does it, as long as DMEM_ADDR_W is 5 or greater:
Guest
#3889992
tb_addr <= (1 => '1', others => '0'); --bit 1 is '1' and other bits are '0' Reply |