MohseN wrote:
> We can use a signal assignment statement with inertial delay to remove
> pulses that are smaller than a certain width.
Thats fairly easy:
1 | o <= i after 100 ns;
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2 | -- or
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3 | o <= inertial i after 100 ns;
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4 | -- or
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5 | o <= i when i'stable(100 ns);
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6 | -- or
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7 | o <= i when i'quiet(100 ns);
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> Using only signal assignment statements, write a code fragment for
> removing positive pulses that are greater than a certain width.
Thats a little more tricky. First this means, that all pulses must be
delayed by this "width", because we cannot look into the future. So
the first step will be to examine the transport arrtibutes of VHDL:
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 |
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4 | entity Attribut is
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5 | Port ( i : in STD_LOGIC;
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6 | o5 : out STD_LOGIC := '0';
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7 | o4 : out STD_LOGIC := '0';
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8 | o3 : out STD_LOGIC := '0';
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9 | o2 : out STD_LOGIC := '0';
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10 | o1 : out STD_LOGIC := '0');
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11 | end Attribut;
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12 |
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13 | architecture Behavioral of Attribut is
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14 | signal h : std_logic;
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15 | begin
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16 | o1 <= i'delayed(100 ns);
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17 | o2 <= i after(100 ns);
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18 | o3 <= i when i'stable(100 ns);
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19 | o4 <= i when i'quiet(100 ns);
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20 |
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21 | h <= i after(100 ns);
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22 | o5 <= i'delayed(100 ns) when h='0' else '0';
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23 | end Behavioral;
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And with a closer view at o1 and o2 its easy to see, that those two
together will lead to the goal. By using a helper signal the input is
passed through only when the inertial delayed input is already low after
100ns. As a result only high pulses shorter than 100ns will pass from i
to o5...
