EmbDev.net

Forum: FPGA, VHDL & Verilog VHDL signal assigment


VHDL signal assigment
von MohseN (Guest)

Rate this post
• ▲ useful
▼ not useful 
this is my question :
We can use a signal assignment statement with inertial delay to remove 
pulses that are smaller than a certain width. Using only signal 
assignment statements, write a code fragment for removing positive 
pulses that are greater than a certain width.
Thanks eveybody :)

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Re: VHDL signal assigment
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

Rate this post
• ▲ useful
▼ not useful 
Real hardware oder simulation?

Report post Edit Delete Quote selected text Reply Reply with quote
Re: VHDL signal assigment
von MohseN (Guest)

Rate this post
• ▲ useful
▼ not useful 
just simulation.

Report post Edit Delete Quote selected text Reply Reply with quote
Re: VHDL signal assigment
von Daniel R. (dan066)

Rate this post
• ▲ useful
▼ not useful 
Maybe something like:
1
if input = '1' then

2
  output <= input after 100 ns;

3
end if;

or
1
 output <= input after 100 when input = '1' else '0';

: Edited by User
Report post Edit Delete Quote selected text Reply Reply with quote
Re: VHDL signal assigment
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

Attached files:
Rate this post
• ▲ useful
▼ not useful 
MohseN wrote:
> We can use a signal assignment statement with inertial delay to remove
> pulses that are smaller than a certain width.
Thats fairly easy:
1
   o <= i after 100 ns;

2
   -- or

3
   o <= inertial i after 100 ns;

4
   -- or

5
   o <= i when i'stable(100 ns);

6
   -- or

7
   o <= i when i'quiet(100 ns);


> Using only signal assignment statements, write a code fragment for
> removing positive pulses that are greater than a certain width.
Thats a little more tricky. First this means, that all pulses must be 
delayed by this "width", because we cannot look into the future. So 
the first step will be to examine the transport arrtibutes of VHDL:
1
library IEEE;

2
use IEEE.STD_LOGIC_1164.ALL;

3
4
entity Attribut is

5
    Port ( i : in  STD_LOGIC;

6
           o5 : out  STD_LOGIC := '0';

7
           o4 : out  STD_LOGIC := '0';

8
           o3 : out  STD_LOGIC := '0';

9
           o2 : out  STD_LOGIC := '0';

10
           o1 : out  STD_LOGIC := '0');

11
end Attribut;

12
13
architecture Behavioral of Attribut is

14
signal h : std_logic;

15
begin

16
   o1 <= i'delayed(100 ns);

17
   o2 <= i after(100 ns);

18
   o3 <= i when i'stable(100 ns);

19
   o4 <= i when i'quiet(100 ns);

20
   

21
   h  <= i after(100 ns);

22
   o5 <= i'delayed(100 ns) when h='0' else '0';

23
end Behavioral;

And with a closer view at o1 and o2 its easy to see, that those two 
together will lead to the goal. By using a helper signal the input is 
passed through only when the inertial delayed input is already low after 
100ns. As a result only high pulses shorter than 100ns will pass from i 
to o5...

  


  



  

  
:
    Edited by Moderator
  

  


  

    Report post Edit Delete Quote selected text Reply Reply with quote
  








    

    

       Watch this topic

      |
         Disable multi-page view

    

        


Please log in before posting. Registration is free and takes only a minute.



  Existing account

  


  
  

  
    

      

        
          
        
        
          
        
      

      

        
          
        
        
          
        
      

    


    
    
    





  Do you have a Google/GoogleMail account? No registration required!

  Log in with Google account
  





  No account? Register here.