Hi Like the title says..Can I get this to work in Verilog? if ((control == 0) and (array == 1) and (value > minvalue) and (value < maxvalue))
Astudentofminewhowasalittlepiggie wrote: > Can I get this to work in Verilog? Whats the problem with it? Do you encounter any problems? Which ones?
Yes, its a compiler error. Error (10170): Verilog HDL syntax error at Graycounter.v(15) near text ";"; expecting ")"
Ofcourse not that, i needed a recompile.. Error (10170): Verilog HDL syntax error at Graycounter.v(15) near text "and"; expecting ")" this one..