Guest
#3897544
Hi Like the title says..Can I get this to work in Verilog? if ((control == 0) and (array == 1) and (value > minvalue) and (value < maxvalue))
Astudentofminewhowasalittlepiggie wrote: > Can I get this to work in Verilog? Whats the problem with it? Do you encounter any problems? Which ones?
Guest
#3897591
Yes, its a compiler error. Error (10170): Verilog HDL syntax error at Graycounter.v(15) near text ";"; expecting ")"
Guest
#3897595
Ofcourse not that, i needed a recompile.. Error (10170): Verilog HDL syntax error at Graycounter.v(15) near text "and"; expecting ")" this one..
Guest
#3897605
The and operator is written as &&, just like in C
Guest
#3897610
Yes, that compiled. thanks!
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