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Forum: FPGA, VHDL & Verilog One bit for status


One bit for status
von Raju (Guest)

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Hi All,

I have 4 registers (for Address, Data_to_be_read, Data_to_be_written & 
Control) in a serial RX block.

This will be accessed by another Serial Tx Master device, it accesses 
the address register, if control is read=1, goes to that address and 
read the data from that address and copies it to Data_to_be_read 
register.

If the control is write=1, it reads the address from Address register, 
copies data from Data_to_be_written register and writes it on to the 
address location.

Now my problem is if i use 1 bit for control register '1' for read and 
'0' for write, it may start reading at correct times, but keeps on 
writing all the time when the bit is '0' . (end of reading not 
necessarily mean writing)

(however if i use two separate 1 bit lines for read and write, i can use 
pulse in those leans to decode when to start reading and when to start 
writing).

Is it possible to use 1 bit for control and still start the reading 
operation and writing operation.

Thank you,

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Re: One bit for status
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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See it that way: you can read every address randomly at every time. 
But you only should write stable data to a valid address. So the 
default of that flag must be: Read.

One problem may occur, when you try to read registers that implicitly 
write something. For example when you read a interrupt register, and 
that read itself resets the interrupt request (as it is in some uC).

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