I am multiplying a 2kHz sinewave with another 100khz sinewave to obtain a dsb-sc signal. These sinewaves were designed using DDS cores. I am also using a 50mHz clock. I would like to demodulate this dsb-sc signal. I am doing this by multiplying the dsb-sc signal with the carrier (100khz signal). Now i have to pass this signal through a low pass filter. I have generated a coefficient file (.coe) from matlab and am using the FIR compiler to actually generate the low pass filter. I have put 50mhz as the input clock frequency but the problem is that i am not exactly sure what to put in as the sampling frequency. Could anyone provide some help regarding this. Thanks a million
Attached files:
The temporal distance between your samples is the sample time. So if you calculate every 1/50M seconds a new output, then 50MHz is your sample frequency. BR
So you are telling me that for both the sampling frequency and clock frequency i should enter 50 mhz?
Roger Swan wrote: > So you are telling me that for both the sampling frequency and clock > frequency i should enter 50 mhz? If you provide a new sample every CLK-Cycle, then the answer is: Yes If you provide a new sample only every nth CLK-Cycle, then the answer is: No. You may e.g. have a sampling rate of 500kHz and a CLK of 50MHz. Then you enter the corresponding numbers and tell the FIR every 100th CLK cycle, that there is a new sample at its input. If think the corresponding pin is named ND (New Data). If your data comes from an external ADC, the sample rate will often be lower than 50MHz. If all your data generation and data handling is done internally in the FPGA, then you could of course provide a new sample every 20ns. But you're the only one who knows. We may only guess...
Watch this topic
Disable multi-page viewPlease log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
Log in with Google account
No account? Register here.