SSD1322 - Clock Cycle Time in 8080 Parallel Mode

Hello All,

The Univision SSD1322 datasheet (OLED 480x256) specifies in 8080 
parallel interface mode a "Clock Cycle Time" (tcycle) of min. 300ns. 
Unfortunately it provides no further explanation on the significance of 
this particular spec.

Looking at the timing diagramm (e.g. 
http://www.hpinfotech.ro/SSD1322.pdf, p. 52/60) tcycle spans for one 
low/high cycle of RW/WR# resp. RD# signal (min. duration 60/60 ns resp. 
150/60 ns plus edge duration). Does this mean that additional delays 
have to be inserted to satisfy overall 300ns tcycle duration on top of 
fulfilling all other timings (low / high time, data setup, data access, 
output invalid etc.)? And if so, where should these be inserted? Does 
this hold for write mode the same as for reading?

Regards,
Burkhard