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Subject Author Replies Last post
Basic Question Elena Cososchi 2
control logic for memory selection felix89 2
OV7670 camera in VHDL jeorges FrenchRivera 6
Multiple posedges in sensitivity list Joe 6
VHDL calculator matrix input help. ed jones 1
Limit current of L6206 Bridge Driver Torsten 5
Please help me in writing correct verilog test bench code for parallel crc32 with 32 bit data width Ajit Sinam 2
Arcade Centipede Game in Verilog Asiong Martinez 11
Bitwise OR of std_logic_vector Hamidreza Ahmadian 2
Inertial sensors not giving updated values Aditya K. 0
STM32F401RE GPIO Asiong Martinez 0
problem in 2d- dct computation Ajay Mittal 1
SAM7-EX256 - /bin/sh: arm-elf-as: command not found Roslan Hristov 0
FATAL_ERROR: Iteration limit 10000 is reached Rohan Narkhede 7
DCT code. Don't know why it is not working. Ajay Mittal 2
recommend me an FPGA card for networking Nulik Nol 4
User Flash Memory, Machxo2 7000HE breakout ChrisChris 2
watermarking on FPGA Hamid Kavian 3
GPS to FPGA to PC Yuniarto Wimbo Nugroho 9
shift left or shift right deepak singh 9
Altium (SVN)DbLib Add/Edit Component in Altium Martin 6
Which step up converter to choose for a fixed Vout independent from Vin Jens Strümper 4
Please Help! Not gate implementation nand Mihai Marius 2
Timing Requirements - Worst case Removal Slack Bryan 1
Interfacing FPGA with Global shutter camrea Mike 5
Openning Serial port - AT91SAM7S265 Shira Meltzer 0
MAC Adresses - sort of refund for shredded Computers? [VSOP]Chateau-Migraine 1
Need help running SSD1322 with ER-OLEDM032-1 OLED Alex Lynchosky 6
GUI for Raspi and Python to deliver Instrument panels Hellmut Kohlsdorf 0
Blocking cammand Implementation Question guitardenver 9
Bandpass Filter Walid Whx 1
Serial data to OBD2 Pezi 0
RAM testing using VHDL Ritu Singh 0
help error 10822 vhdl daniel 1
Help with code for SPGA Vadhiraj 2
how to use clk in fsm daniel 2
Wrong value received in SPI receive register Aditya K. 4
8 bit serial to parallel Rushin thakkar 5
Parameterizing a data type in SystemVerilog/Verilog Joshua Vasquez 0
UART with Adder Maxim Moor 4
counting length of input signal in clock cycle units Counting length of input signal 1
VHDL synthesis result is not equal to behavioral Michal 4
Microcontroller for game controller Max Frank 5
Verilog VGA code HS VS timing Keny Joneyer 7
Can protocol to FPGA Ba Ehb 17
Connect 2 FIFOs and pass data [xillybus - VHDL] Junior Hpc 0
E:5 SMD CODE SOT23-5 reza 1
Does Verilog have generic map like VHDL? Sean Zheng 4
Voltage ThrEshold Adaptive Memristor in verilog Ronny Josef 0
Booting the PPC440 in virtex 5 processor from strata flash in ML507 development board Venkatesh 1
looking for the MIPS1 PH project v2 Legacy My 45