I am working now on implementing a 16 bit RISC CPU in VHDL, the 
instruction set consists of 8 instructions 16 bits each.
the architecture of the data path and instruction flow is here, i need 
your help how to start implementation? could you give me examples for 
source codes like this architectur

All I can say is that you should try to make a feature list and some 
test cases for each submodule to make yourself clear what you should 
implement and then go on from there...

There are hundreds of custom CPUs on the net you just have to search a 
bit. I found this PDF very helpful: 
http://opencores.org/usercontent,doc,1262702554