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Forum: FPGA, VHDL & Verilog Storing char application


von Junior H. (Company: University) (junior_hpc)


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Hello. I want to develop an application that is able to get and store 
two input values, swap from lower case to upper case only the first 
value and finally output the two stored values. E.g.: if the input 
string is "john", then the output string should be "JoHn". The 
application should get "j" from user_w_write_8_data and store it into 
my_buffer_a, swap "j" into "J", then get "o" store it into my_buffer_b, 
then output "J", then output "o". After that the application should get 
"h" from user_w_write_8_data,  swap "h" into "H", and store it into 
my_buffer_a, then get "n" store it into my_buffer_b, then output "H", 
then output "n". Basically, the application should store two characters, 
swap the first one and then output these two, store other two 
characters, swap the first one and then output these two characters etc. 
The problem of my application does not swap lower to upper characters 
that is stored into my_buffer_a. Instead of outputing "JoHn", my 
application outputs "john". It seems like that my application does not 
go into the first if statement (if (counter=0) then...), but I am asking 
to myself how it is possible that the application outputs data if does 
not go into if (counter=0) then... Any hint?

Thanks.

Here the code:
1
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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6
entity xillydemo is
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  port (
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    PCIE_PERST_B_LS : IN std_logic;
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    PCIE_REFCLK_N : IN std_logic;
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    PCIE_REFCLK_P : IN std_logic;
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    PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);
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    PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);
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    GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
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    PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);
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    PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0));
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end xillydemo;
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architecture sample_arch of xillydemo is
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  component xillybus
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    port (
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      PCIE_PERST_B_LS : IN std_logic;
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      PCIE_REFCLK_N : IN std_logic;
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      PCIE_REFCLK_P : IN std_logic;
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      PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);
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      PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);
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      GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
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      PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);
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      PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0);
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      bus_clk : OUT std_logic;
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      quiesce : OUT std_logic;
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      user_r_mem_8_rden : OUT std_logic;
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      user_r_mem_8_empty : IN std_logic;
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      user_r_mem_8_data : IN std_logic_vector(7 DOWNTO 0);
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      user_r_mem_8_eof : IN std_logic;
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      user_r_mem_8_open : OUT std_logic;
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      user_w_mem_8_wren : OUT std_logic;
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      user_w_mem_8_full : IN std_logic;
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      user_w_mem_8_data : OUT std_logic_vector(7 DOWNTO 0);
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      user_w_mem_8_open : OUT std_logic;
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      user_mem_8_addr : OUT std_logic_vector(4 DOWNTO 0);
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      user_mem_8_addr_update : OUT std_logic;
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      user_r_read_32_rden : OUT std_logic;
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      user_r_read_32_empty : IN std_logic;
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      user_r_read_32_data : IN std_logic_vector(31 DOWNTO 0);
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      user_r_read_32_eof : IN std_logic;
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      user_r_read_32_open : OUT std_logic;
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      user_r_read_8_rden : OUT std_logic;
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      user_r_read_8_empty : IN std_logic;
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      user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);
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      user_r_read_8_eof : IN std_logic;
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      user_r_read_8_open : OUT std_logic;
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      user_w_write_32_wren : OUT std_logic;
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      user_w_write_32_full : IN std_logic;
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      user_w_write_32_data : OUT std_logic_vector(31 DOWNTO 0);
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      user_w_write_32_open : OUT std_logic;
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      user_w_write_8_wren : OUT std_logic;
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      user_w_write_8_full : IN std_logic;
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      user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);
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      user_w_write_8_open : OUT std_logic);
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  end component;
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  component fifo_8x2048
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    port (
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      clk: IN std_logic;
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      srst: IN std_logic;
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      din: IN std_logic_VECTOR(7 downto 0);
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      wr_en: IN std_logic;
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      rd_en: IN std_logic;
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      dout: OUT std_logic_VECTOR(7 downto 0);
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      full: OUT std_logic;
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      empty: OUT std_logic);
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  end component;
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  component fifo_32x512
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    port (
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      clk: IN std_logic;
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      srst: IN std_logic;
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      din: IN std_logic_VECTOR(31 downto 0);
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      wr_en: IN std_logic;
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      rd_en: IN std_logic;
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      dout: OUT std_logic_VECTOR(31 downto 0);
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      full: OUT std_logic;
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      empty: OUT std_logic);
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  end component;
85
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-- Synplicity black box declaration
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  attribute syn_black_box : boolean;
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  attribute syn_black_box of fifo_32x512: component is true;
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  attribute syn_black_box of fifo_8x2048: component is true;
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  type demo_mem is array(0 TO 31) of std_logic_vector(7 DOWNTO 0);
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  signal demoarray : demo_mem;
93
  
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  signal bus_clk :  std_logic;
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  signal quiesce : std_logic;
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  signal reset_8 : std_logic;
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  signal reset_32 : std_logic;
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  signal ram_addr : integer range 0 to 31;
101
  
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  signal user_r_mem_8_rden :  std_logic;
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  signal user_r_mem_8_empty :  std_logic;
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  signal user_r_mem_8_data :  std_logic_vector(7 DOWNTO 0);
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  signal user_r_mem_8_eof :  std_logic;
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  signal user_r_mem_8_open :  std_logic;
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  signal user_w_mem_8_wren :  std_logic;
108
  signal user_w_mem_8_full :  std_logic;
109
  signal user_w_mem_8_data :  std_logic_vector(7 DOWNTO 0);
110
  signal user_w_mem_8_open :  std_logic;
111
  signal user_mem_8_addr :  std_logic_vector(4 DOWNTO 0);
112
  signal user_mem_8_addr_update :  std_logic;
113
  signal user_r_read_32_rden :  std_logic;
114
  signal user_r_read_32_empty :  std_logic;
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  signal user_r_read_32_data :  std_logic_vector(31 DOWNTO 0);
116
  signal user_r_read_32_eof :  std_logic;
117
  signal user_r_read_32_open :  std_logic;
118
  signal user_r_read_8_rden :  std_logic;
119
  signal user_r_read_8_empty :  std_logic;
120
  signal user_r_read_8_data :  std_logic_vector(7 DOWNTO 0);
121
  signal user_r_read_8_eof :  std_logic;
122
  signal user_r_read_8_open :  std_logic;
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  signal user_w_write_32_wren :  std_logic;
124
  signal user_w_write_32_full :  std_logic;
125
  signal user_w_write_32_data :  std_logic_vector(31 DOWNTO 0);
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  signal user_w_write_32_open :  std_logic;
127
  signal user_w_write_8_wren :  std_logic;
128
  signal user_w_write_8_full :  std_logic;
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  signal user_w_write_8_data :  std_logic_vector(7 DOWNTO 0);
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  signal user_w_write_8_open :  std_logic;
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132
begin
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  xillybus_ins : xillybus
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    port map (
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      -- Ports related to /dev/xillybus_mem_8
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      -- FPGA to CPU signals:
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      user_r_mem_8_rden => user_r_mem_8_rden,
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      user_r_mem_8_empty => user_r_mem_8_empty,
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      user_r_mem_8_data => user_r_mem_8_data,
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      user_r_mem_8_eof => user_r_mem_8_eof,
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      user_r_mem_8_open => user_r_mem_8_open,
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      -- CPU to FPGA signals:
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      user_w_mem_8_wren => user_w_mem_8_wren,
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      user_w_mem_8_full => user_w_mem_8_full,
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      user_w_mem_8_data => user_w_mem_8_data,
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      user_w_mem_8_open => user_w_mem_8_open,
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      -- Address signals:
148
      user_mem_8_addr => user_mem_8_addr,
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      user_mem_8_addr_update => user_mem_8_addr_update,
150
151
      -- Ports related to /dev/xillybus_read_32
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      -- FPGA to CPU signals:
153
      user_r_read_32_rden => user_r_read_32_rden,
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      user_r_read_32_empty => user_r_read_32_empty,
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      user_r_read_32_data => user_r_read_32_data,
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      user_r_read_32_eof => user_r_read_32_eof,
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      user_r_read_32_open => user_r_read_32_open,
158
159
      -- Ports related to /dev/xillybus_read_8
160
      -- FPGA to CPU signals:
161
      user_r_read_8_rden => user_r_read_8_rden,
162
      user_r_read_8_empty => user_r_read_8_empty,
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      user_r_read_8_data => user_r_read_8_data,
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      user_r_read_8_eof => user_r_read_8_eof,
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      user_r_read_8_open => user_r_read_8_open,
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167
      -- Ports related to /dev/xillybus_write_32
168
      -- CPU to FPGA signals:
169
      user_w_write_32_wren => user_w_write_32_wren,
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      user_w_write_32_full => user_w_write_32_full,
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      user_w_write_32_data => user_w_write_32_data,
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      user_w_write_32_open => user_w_write_32_open,
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174
      -- Ports related to /dev/xillybus_write_8
175
      -- CPU to FPGA signals:
176
      user_w_write_8_wren => user_w_write_8_wren,
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      user_w_write_8_full => user_w_write_8_full,
178
      user_w_write_8_data => user_w_write_8_data,
179
      user_w_write_8_open => user_w_write_8_open,
180
181
      -- General signals
182
      PCIE_PERST_B_LS => PCIE_PERST_B_LS,
183
      PCIE_REFCLK_N => PCIE_REFCLK_N,
184
      PCIE_REFCLK_P => PCIE_REFCLK_P,
185
      PCIE_RX_N => PCIE_RX_N,
186
      PCIE_RX_P => PCIE_RX_P,
187
      GPIO_LED => GPIO_LED,
188
      PCIE_TX_N => PCIE_TX_N,
189
      PCIE_TX_P => PCIE_TX_P,
190
      bus_clk => bus_clk,
191
      quiesce => quiesce
192
      );
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194
--  A simple inferred RAM
195
196
  ram_addr <= conv_integer(user_mem_8_addr);
197
  
198
  process (bus_clk)
199
        
200
            variable counter : integer := 0;
201
            variable my_buffer_a :  std_logic_vector(7 downto 0) := (others => '0');
202
            variable my_buffer_b :  std_logic_vector(7 downto 0) := (others => '0');
203
            
204
            begin 
205
              
206
              if (bus_clk'event and bus_clk = '1') then
207
                 if (counter=0) then --push data from user_w_write_8_data to my_buffer_a
208
                    my_buffer_a := user_w_write_8_data;
209
                    my_buffer_a(5) := not my_buffer_a(5);
210
                    counter := 1;
211
                 elsif (counter = 1) then --push data from user_w_write_8_data to my_buffer_b
212
                    my_buffer_b := user_w_write_8_data;
213
                    counter := 2;
214
                 elsif (counter = 2) then --pull data from my_buffer_a to din
215
                    user_r_mem_8_data <= my_buffer_a;
216
                    counter := 3;
217
                 elsif (counter = 3) then --pull data from my_buffer_b to din
218
                    user_r_mem_8_data <= my_buffer_b;
219
                    counter := 0;
220
                 end if;
221
             end if;
222
         end process;
223
224
  user_r_mem_8_empty <= '0';
225
  user_r_mem_8_eof <= '0';
226
  user_w_mem_8_full <= '0';
227
228
--  32-bit loopback
229
230
  fifo_32 : fifo_32x512
231
    port map(
232
      clk        => bus_clk,
233
      srst       => reset_32,
234
      din        => user_w_write_32_data,
235
      wr_en      => user_w_write_32_wren,
236
      rd_en      => user_r_read_32_rden,
237
      dout       => user_r_read_32_data,
238
      full       => user_w_write_32_full,
239
      empty      => user_r_read_32_empty
240
      );
241
242
  reset_32 <= not (user_w_write_32_open or user_r_read_32_open);
243
244
  user_r_read_32_eof <= '0';
245
  
246
--  8-bit loopback
247
248
  fifo_8 : fifo_8x2048
249
    port map(
250
      clk        => bus_clk,
251
      srst       => reset_8,
252
      din        => user_w_write_8_data,
253
      wr_en      => user_w_write_8_wren,
254
      rd_en      => user_r_read_8_rden,
255
      dout       => user_r_read_8_data,
256
      full       => user_w_write_8_full,
257
      empty      => user_r_read_8_empty
258
      );
259
260
    reset_8 <= not (user_w_write_8_open or user_r_read_8_open);
261
262
    user_r_read_8_eof <= '0';
263
  
264
end sample_arch;

von S. N. (higgns)


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The code looks fine. In your previous thread you were writing into the 
FIFO instead of mem_8_data though.

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