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char count application
von Junior H. (Company: University) (junior_hpc)

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Hello. I have developed a char count application. Basically, this 
application counts the number of "a" chars given in the input file and 
it outputs the total number of "a" chars.

Here my code:
1
library ieee;

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use ieee.std_logic_1164.all;

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use ieee.std_logic_unsigned.all;

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use ieee.numeric_std.all;

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entity xillydemo is

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  port (

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     PCIE_PERST_B_LS : IN std_logic;

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     PCIE_REFCLK_N : IN std_logic;

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     PCIE_REFCLK_P : IN std_logic;

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     PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);

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     PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);

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     GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);

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     PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);

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     PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0));

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end xillydemo;

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architecture sample_arch of xillydemo is

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    signal tmp :  std_logic_vector(7 DOWNTO 0);

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  component xillybus

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    port (

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      PCIE_PERST_B_LS : IN std_logic;

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      PCIE_REFCLK_N : IN std_logic;

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      PCIE_REFCLK_P : IN std_logic;

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      PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);

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      PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);

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      GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);

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      PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);

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      PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0);

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      bus_clk : OUT std_logic;

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      quiesce : OUT std_logic;

34
      

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      user_r_read_8_rden : OUT std_logic;

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      user_r_read_8_empty : IN std_logic;

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      user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);

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      user_r_read_8_eof : IN std_logic;

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      user_r_read_8_open : OUT std_logic;

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      user_w_write_8_wren : OUT std_logic;

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      user_w_write_8_full : IN std_logic;

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      user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);

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      user_w_write_8_open : OUT std_logic);

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  end component;

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  component fifo_8x2048

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    port (

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      clk: IN std_logic;

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      srst: IN std_logic;

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      din: IN std_logic_VECTOR(7 downto 0);

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      char_a: IN integer;

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      wr_en: IN std_logic;

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      rd_en: IN std_logic;

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      dout: OUT std_logic_VECTOR(7 downto 0);

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      full: OUT std_logic;

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      empty: OUT std_logic);

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  end component;

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59
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-- Synplicity black box declaration

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  attribute syn_black_box : boolean;

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  attribute syn_black_box of fifo_8x2048: component is true;

63
  

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  signal bus_clk :  std_logic;

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  signal quiesce : std_logic;

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  signal reset_8 : std_logic;

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  signal ram_addr : integer range 0 to 31;

70
 

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  signal user_r_read_8_rden  :  std_logic;

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  signal user_r_read_8_empty :  std_logic;

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  signal user_r_read_8_data  :  std_logic_vector(7 DOWNTO 0);

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  signal user_r_read_8_eof   :  std_logic;

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  signal user_r_read_8_open  :  std_logic;

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  signal user_w_write_8_wren :  std_logic;

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  signal user_w_write_8_full :  std_logic;

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  signal user_w_write_8_data :  std_logic_vector(7 DOWNTO 0);

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  signal user_w_write_8_open :  std_logic;

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  signal wr_en               :  std_logic := '0';

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  signal din                 :  std_logic_vector(user_w_write_8_data'range) := (others => '0');

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  signal char_a              :  integer := 0;

83
  

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begin

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  xillybus_ins : xillybus

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    port map (

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      -- Ports related to /dev/xillybus_read_8

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      -- FPGA to CPU signals:

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      user_r_read_8_rden => user_r_read_8_rden,

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      user_r_read_8_empty => user_r_read_8_empty,

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      user_r_read_8_data => user_r_read_8_data,

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      user_r_read_8_eof => user_r_read_8_eof,

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      user_r_read_8_open => user_r_read_8_open,

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      -- Ports related to /dev/xillybus_write_8

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      -- CPU to FPGA signals:

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      user_w_write_8_wren => user_w_write_8_wren,

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      user_w_write_8_full => user_w_write_8_full,

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      user_w_write_8_data => user_w_write_8_data,

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      user_w_write_8_open => user_w_write_8_open,

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      -- General signals

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      PCIE_PERST_B_LS => PCIE_PERST_B_LS,

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      PCIE_REFCLK_N => PCIE_REFCLK_N,

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      PCIE_REFCLK_P => PCIE_REFCLK_P,

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      PCIE_RX_N => PCIE_RX_N,

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      PCIE_RX_P => PCIE_RX_P,

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      GPIO_LED => GPIO_LED,

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      PCIE_TX_N => PCIE_TX_N,

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      PCIE_TX_P => PCIE_TX_P,

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      bus_clk => bus_clk,

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      quiesce => quiesce

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   );

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  process (bus_clk)

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  begin 

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            wr_en <= user_w_write_8_wren;

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            user_r_read_8_eof <= user_r_read_8_empty and not(user_w_write_8_open);

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            if (user_w_write_8_data="01100001") then --a

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                char_a <= char_a + 1;

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            end if; 

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  end process;

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--  8-bit loopback

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  fifo_8 : fifo_8x2048

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    port map(

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          clk        => bus_clk,

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          srst       => reset_8,

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          din        => din,

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          wr_en      => wr_en,

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          rd_en      => user_r_read_8_rden,

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          dout       => user_r_read_8_data,

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          full       => user_w_write_8_full,

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          empty      => user_r_read_8_empty,

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          char_a     => char_a

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      );

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    reset_8 <= not (user_w_write_8_open or user_r_read_8_open);

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end sample_arch;


I added the signal char_a (integer) that every time user_w_write_8_data 
contains "a" (01100001), char_a increments of 1. The problem is that 
Vivado does not like char_a, because it says:
1
[Netlist 29-77] Could not replace (cell 'fifo_8x2048', library 'work', file 'xillydemo.edf') with (cell 'fifo_8x2048', library 'work', file 'fifo_8x2048.edf') because of a port interface mismatch; 32 ports are missing on the replacing cell. 5 of the missing ports are: 'char_a[31]' 'char_a[30]' 'char_a[29]' 'char_a[1]' 'char_a[0]'.


It seems like I have to define char_a signal somewhere else, but I don't 
know where. Any hint?

Thanks.

  


  




  

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    Re: char count application
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Junior H. wrote:
> attribute syn_black_box of fifo_8x2048: component is true;
(How) did you adapt this Xilinx blackbox "fifo_8x2048"?

  


  




  

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