char count application

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

entity xillydemo is

  port (

     PCIE_PERST_B_LS : IN std_logic;

     PCIE_REFCLK_N : IN std_logic;

     PCIE_REFCLK_P : IN std_logic;

     PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);

     PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);

     GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);

     PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);

     PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0));

end xillydemo;

architecture sample_arch of xillydemo is

    signal tmp :  std_logic_vector(7 DOWNTO 0);

  component xillybus

    port (

      PCIE_PERST_B_LS : IN std_logic;

      PCIE_REFCLK_N : IN std_logic;

      PCIE_REFCLK_P : IN std_logic;

      PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);

      PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);

      GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);

      PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);

      PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0);

      bus_clk : OUT std_logic;

      quiesce : OUT std_logic;

      user_r_read_8_rden : OUT std_logic;

      user_r_read_8_empty : IN std_logic;

      user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);

      user_r_read_8_eof : IN std_logic;

      user_r_read_8_open : OUT std_logic;

      user_w_write_8_wren : OUT std_logic;

      user_w_write_8_full : IN std_logic;

      user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);

      user_w_write_8_open : OUT std_logic);

  end component;

  component fifo_8x2048

    port (

      clk: IN std_logic;

      srst: IN std_logic;

      din: IN std_logic_VECTOR(7 downto 0);

      char_a: IN integer;

      wr_en: IN std_logic;

      rd_en: IN std_logic;

      dout: OUT std_logic_VECTOR(7 downto 0);

      full: OUT std_logic;

      empty: OUT std_logic);

  end component;

-- Synplicity black box declaration

  attribute syn_black_box : boolean;

  attribute syn_black_box of fifo_8x2048: component is true;

  signal bus_clk :  std_logic;

  signal quiesce : std_logic;

  signal reset_8 : std_logic;

  signal ram_addr : integer range 0 to 31;

  signal user_r_read_8_rden  :  std_logic;

  signal user_r_read_8_empty :  std_logic;

  signal user_r_read_8_data  :  std_logic_vector(7 DOWNTO 0);

  signal user_r_read_8_eof   :  std_logic;

  signal user_r_read_8_open  :  std_logic;

  signal user_w_write_8_wren :  std_logic;

  signal user_w_write_8_full :  std_logic;

  signal user_w_write_8_data :  std_logic_vector(7 DOWNTO 0);

  signal user_w_write_8_open :  std_logic;

  signal wr_en               :  std_logic := '0';

  signal din                 :  std_logic_vector(user_w_write_8_data'range) := (others => '0');

  signal char_a              :  integer := 0;

begin

  xillybus_ins : xillybus

    port map (

      -- Ports related to /dev/xillybus_read_8

      -- FPGA to CPU signals:

      user_r_read_8_rden => user_r_read_8_rden,

      user_r_read_8_empty => user_r_read_8_empty,

      user_r_read_8_data => user_r_read_8_data,

      user_r_read_8_eof => user_r_read_8_eof,

      user_r_read_8_open => user_r_read_8_open,

      -- Ports related to /dev/xillybus_write_8

      -- CPU to FPGA signals:

      user_w_write_8_wren => user_w_write_8_wren,

      user_w_write_8_full => user_w_write_8_full,

      user_w_write_8_data => user_w_write_8_data,

      user_w_write_8_open => user_w_write_8_open,

      -- General signals

      PCIE_PERST_B_LS => PCIE_PERST_B_LS,

      PCIE_REFCLK_N => PCIE_REFCLK_N,

      PCIE_REFCLK_P => PCIE_REFCLK_P,

      PCIE_RX_N => PCIE_RX_N,

      PCIE_RX_P => PCIE_RX_P,

      GPIO_LED => GPIO_LED,

      PCIE_TX_N => PCIE_TX_N,

      PCIE_TX_P => PCIE_TX_P,

      bus_clk => bus_clk,

      quiesce => quiesce

   );

  process (bus_clk)

  begin 

            wr_en <= user_w_write_8_wren;

            user_r_read_8_eof <= user_r_read_8_empty and not(user_w_write_8_open);

            if (user_w_write_8_data="01100001") then --a

                char_a <= char_a + 1;

            end if; 

  end process;

--  8-bit loopback

  fifo_8 : fifo_8x2048

    port map(

          clk        => bus_clk,

          srst       => reset_8,

          din        => din,

          wr_en      => wr_en,

          rd_en      => user_r_read_8_rden,

          dout       => user_r_read_8_data,

          full       => user_w_write_8_full,

          empty      => user_r_read_8_empty,

          char_a     => char_a

      );

    reset_8 <= not (user_w_write_8_open or user_r_read_8_open);

end sample_arch;

[Netlist 29-77] Could not replace (cell 'fifo_8x2048', library 'work', file 'xillydemo.edf') with (cell 'fifo_8x2048', library 'work', file 'fifo_8x2048.edf') because of a port interface mismatch; 32 ports are missing on the replacing cell. 5 of the missing ports are: 'char_a[31]' 'char_a[30]' 'char_a[29]' 'char_a[1]' 'char_a[0]'.