# Forum: FPGA, VHDL & Verilog Active-HDL design

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Hi i have ptoblem with this code, it dosent work corectly with big
data(number). For example p1=< 28623421, sqrt1 >= p1. Can eny one help
me?

 if sqrt(sqrt1) mod 1.0/= 0.0 then while sqrt(sqrt1+k1*p1) mod 1.0 /= 0.0 loop k1<=k1+1.0; exit when sqrt(sqrt1+k1*p1) mod 1.0 > 0.0; end loop; g1<=sqrt(sqrt1+k1*p1) mod p1; else g1<=sqrt(sqrt1)mod p1; end if; 

: Edited by User

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Nazar R. wrote:
> Can eny one help me?
1.) Read the manual of the edit box:
 Reply Rules — please read before posting : Formatting options : [vhdl]VHDL code[/vhdl] 

2.) Use indention and advanced formatting to get a readable code.
 if sqrt(sqrt1) mod 1.0/= 0.0 then while sqrt(sqrt1+k1*p1) mod 1.0 /= 0.0 loop k1<=k1+1.0; exit when sqrt(sqrt1+k1*p1) mod 1.0 > 0.0; end loop; g1<=sqrt(sqrt1+k1*p1) mod p1; else g1<=sqrt(sqrt1)mod p1; end if; 

3.) What data types have the used signals?
Integer? Real?

> p1=< 28623421
What is "p1"? Is it the input parameter for the incomplete function or
the unknown process?

> For example p1=< 28623421, sqrt1 >= p1.
What does that mean? What do you expect? What do you get instead? And
HOW do you get that?

Simply attach the complete *.vhd file...

: Edited by Moderator

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p1 is a input data, real character, as the sqrt1 value

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its all the part of math expression, in this part i have problem with
get sqrt function

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Nazar R. wrote:
> it dosent work corectly with big data(number). For example p1=<
> 28623421, sqrt1 >= p1. Can eny one help me?
I suppose you simply have a problem with the number of significant
digits of a real number.
See that: http://codepad.org/s4xolHhg

: Edited by Moderator

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no youa wrone. i know how to write real data type. this part of code
must work with real type because sqrt function work only on this type

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i have just a code problem with loop statment

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Nazar R. wrote:
> this part of code must work with real type
What figures/value/nubmers have those parameters?

Or the other way: show your complete code and the corresponding test
bench. Otherwise we will not get a point here...  :-/

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this is my diagram

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value, parameters i wrote uper this page. this p1.. you need just put
into the program

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> while sqrt(sqrt1+k1*p1) mod 1.0 /= 0.0
Thats the problem: never ever check real values for equality...

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why? if you try to write this sentens into the paper and do some math
you have tru answer. in this line i do some chek, if sqrt1... after do
mod operation exit the 0 state

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mod is defined for integers but not for real.

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but it works for real type isnt?

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Nazar R. wrote:
> but it works for real type isnt?

Check it out for yourselves, I think "x mod 1" gets always zero :

https://en.wikipedia.org/wiki/Modulo_operation

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out of the mist wrote:
> mod is defined for integers but not for real.
Only in C...

But look at this:

A float value nearly never is something like .0000000!
Its more something like .00001 or .999999
Nearly never the result of that operation will be 0.0

: Edited by Moderator

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Lothar M. wrote:
> out of the mist wrote:
>> mod is defined for integers but not for real.
> Only in C...
>

No,
http://www.csee.umbc.edu/portal/help/VHDL/operator.html

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Have a close look for the math_real package:

  function "MOD" (X, Y: in REAL ) return REAL; -- Purpose: -- Returns floating point modulus of X/Y, with the same sign as -- Y, and absolute value less than the absolute value of Y, and -- for some INTEGER value N the result satisfies the relation -- X = Y*N + MOD(X,Y) -- Special values: -- None -- Domain: -- X in REAL; Y in REAL and Y /= 0.0 -- Error conditions: -- Error if Y = 0.0 -- Range: -- ABS(MOD(X,Y)) < ABS(Y) -- Notes: -- None 

: Edited by Moderator

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Hi Nazar,

sqrt(sqrt1) mod 1.0  is almost ALWAYS  unequal  0.0 if  sqrt1  is a
floating point number.

Try  1.0 mod  1.0  and  0.9999999999  mod  1.0
and let  us  know  the result

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thats a point to catch the number when sqrt1 have 0.0.

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in my work i use real type bacause i use sqrt operators a lot of time,
thets why i convert all of my variables to real from integer type. all
operations in the my model give me result in some sing like that 100.0,
152.0, 343558137.0

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Martin wrote:
> mod 1.0 is almost ALWAYS unequal 0.0
Or the other way: NEVER EVER compare a float value to equality

Even if two float numbers "look" the same, they may be different:

Nazar R. wrote:
> all operations in the my model give me result in some sing like that
> 100.0, 152.0, 343558137.0
No, they don't. Think about that, its a "problem" of how a real value is
defined in IEEE 754.

: Edited by Moderator

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write in the calc 123 mod 1 and you have 0 but if you input 123.5 exit
number is cheged. f**ck i dont know how discribe you my problem

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in the line sqrt(sqrt1+k1*p1) outputs may take value like 12.5,
1427.333. thets why i wrote mod 1

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i must get full number without floating data *.45

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Nazar R. wrote:
> write in the calc
In which one?

> 123 mod 1
The mod function is NOT the problem here.

> i dont know how discribe you my problem
Looks alike...

Nazar R. wrote:
> all operations in the my model give me result in some sing like that
> 100.0, 152.0, 343558137.0
Where do you see this values?

For those .0 values have a look there:
You CANNOT compare a float number for equality...

: Edited by Moderator

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do you have active-hdl?

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Nazar R. wrote:
> do you have active-hdl?
Yes. Active HDL also uses the IEE 754 format. And therefore it also has
the same restrictions...

> do you have active-hdl?
But as I already said several times: post your complete VHDL file (as
a *.vhd or *.vhdl file pls!) and the test bench so everybody else can
test your specific problem on his simulator. You can attach several
files to one post...

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sorry i attach only bench file before

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> use IEEE.std_logic_unsigned.all;
> use IEEE.std_logic_signed.all;
> use ieee.numeric_std.all;
> use IEEE.std_logic_arith.all;
Ouch, ouch, ouch, ouch...

EITHER use the use numeric_std (best and preferred choice)
OR use those two: std_logic_signed and std_logic_arith
OR use those two: std_logic_unsigned and std_logic_arith
BUT do NOT use all of them together. Otherwise you have multiple type
definitions and therfore sometimes very weird behaviour...

Nazar R. wrote:
> sorry i attach only bench file before
A test bench usually is a *.vhd module WITHOUT ports in the entity. I
will have a look at that tomorrow, now I'm away for the night... ;-)

: Edited by Moderator

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The entity has only one input but no output.
You use conflicting IEEE packages.
But the main problem is comparing float as Lothar has told you.

Will the compare for equality ever return true? When? Only when it is
exactly equal which might be very rare. You could compare if the float
value is in a given range. E.g. if the value is greater 0.0 and smaller
0.1.

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This will never happen:
> exit when sqrt(sqrt1+k1*p1) mod 1.0 > 1.0;
Something mod 1.0 is always less then 1.0
Therefore this "exit" is useless and obsolete.

I took your code and transferred it into a little bit more handy test
bench. My conclusion: I can se no sense in those calculations. With the
values in the code I have 1.5 million loop iterations...

So the big question is:
What should this code do? Whats the origin of this code? Whats its
purpose?

: Edited by Moderator

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You may also try this in your simulator:
 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.math_real.ALL; entity tb_real_test is end tb_real_test; architecture Behave of tb_real_test is signal a : real := 23456789.0; begin process (a) variable j : real; begin j := sqrt(12100.0); if a=a*j/111.0 then report "a) equal!"; else report "a) different!"; end if; if a mod 1.0 = 0.0 then report "1. remainder is zero!"; end if; if a*j/111.0 mod 1.0 = 0.0 then report "2. remainder is zero!"; end if; j := 111.1; if a=a*j/111.1 then report "b) equal!"; else report "b) different!"; end if; if a*j/111.1 mod 1.0 = 0.0 then report "3. remainder is zero!"; end if; j:=a*j/111.1 mod 1.0; report "Should be .0 --> " & real'image(j); end process; end; 
Think about the results...

: Edited by Moderator

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So, let's again. I am engaged in developing advanced algorithm Rabin
among Atstsdf. Part of my code should find the square root of a number.
Do I have to check this number due to the fact that this number must
then be multiplied by the transaction module and there should get an
integer. small numbers I come out all right, here's an example I attach
a file, it should just run. I ask if large numbers fixate the process of
calculating and never stops

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Nazar R. wrote:
> I am engaged in developing advanced algorithm Rabin among Atstsdf.
Must this code be implemented on a FPGA in future? Then forget about
real...

> here's an example I attach a file, it should just run.
And what should happen?

> here's an example I attach a file, it should just run.
Attach a second one that doesn't "run". And tell how you can see that...

> exit when sqrt(sqrt1+k1*p1) mod 1.0 < 1.0;
Something mod 1.0 is ALWAYS less then 1.0, so here the loop will ALWAYS
be terminated...

Did you read the post https://embdev.net/topic/384548#4390186
Did you understand it?

Let me say it this way: I've shown you some major design flaws and you
ignored all of that hints. I've also shown you a way to set up a
little bit more "talky" test bench and you dig further on with your
code. What do you expect as "help"?

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