von
Joe Joe (Guest)
2015-12-10 18:01
Hello All I have multiple questions for a project for school I am
currently using the Nexys 2 board I have to create a traffic light
controller. I was wondering about a few things that my teacher did not
go over.
The first one is: How do you make multiple LEDs blink such that it would
repeat in a traffic light simulation such as 5 seconds red, 3 seconds
yellow, 1 second green.
My second question is how do you get a countdown to be displayed on the
seven segment display on a Nexys 2 board?
my third question is how do you use the enable line in the program?
This is the code I have so far 1 // Joseph Abel
2 // display same as Y
3 // bits same as L
4 module Top_Mod ( clk , enable , reset , display , bits );
5
6 input clk , reset , enable ;
7 output [ 6 : 0 ] display ;
8 output [ 3 : 0 ] bits ;
9
10 wire [ 2 : 0 ] num ;
11 wire [ 7 : 0 ] output_val ;
12 wire [ 3 : 0 ] sev ;
13 wire [ 6 : 0 ] display_val ;
14 wire clock ;
15 output_result O2 ( output_val , num , clock );
16 multiplexing M3 ( sev , bits , clock , output_val [ 7 : 4 ] , output_val [ 3 : 0 ] );
17 Seven_segment S4 ( display_val , sev );
18 clockslow C5 ( clk , clock , reset );
19
20 assign display = display_val ;
21
22 endmodule
1 module multiplexing ( seg , light , clock , M , L );
2 input clock ;
3 input [ 3 : 0 ] M ;
4 input [ 3 : 0 ] L ;
5
6 output reg [ 3 : 0 ] seg ;
7 output reg [ 3 : 0 ] light ;
8 reg select ;
9
10 always @ ( clock ) // generates a signal that performs multiplexing
11 begin
12 select = ~ clock ;
13 end
14
15 always @ ( clock )
16 case ( select ) // display MSB when select = 0
17 0 :
18 begin
19 select = M ;
20 light = 4 'b1110 ;
21 end
22
23 1 :
24 begin
25
26 select = L ;
27 light = 4 'b1101 ;
28
29 end
30 endcase
31
32 endmodule
1 module Seven_segment ( seven , val );
2 input [ 3 : 0 ] val ;
3 output reg [ 6 : 0 ] seven ;
4 always @ ( val )
5 begin
6 case ( val )
7 0 : seven = 7 'b1000000 ;
8 1 : seven = 7 'b1111001 ;
9 2 : seven = 7 'b0100100 ;
10 3 : seven = 7 'b0110000 ;
11 4 : seven = 7 'b0011001 ;
12 5 : seven = 7 'b0010010 ;
13 6 : seven = 7 'b0000010 ;
14 7 : seven = 7 'b1111000 ;
15 8 : seven = 7 'b0000000 ;
16 9 : seven = 7 'b0011000 ;
17 default : seven = 7 'b1000000 ;
18 endcase
19 end
20 endmodule
21 [\ vhdl ]
22
23 [ vhdl ]
24 module clockslow ( clk , clkreturn , reset );
25
26 input clk , reset ;
27 output clkreturn ;
28 wire clk_50Mhz ;
29 wire clk_100000hz ;
30 wire clk_10000hz ;
31 wire clk_1000hz ;
32 wire clk_100hz ;
33 wire clk_10hz ;
34 wire clk_1hz ;
35
36 assign clkreturn = clk_1hz ;
37
38 divide_50 d6 ( clk_50Mhz , clk , reset );
39 divide_10 d5 ( clk_100000hz , clk_50Mhz , reset );
40 divide_10 d4 ( clk_10000hz , clk_1000000hz , reset );
41 divide_10 d3 ( clk_1000hz , clk_10000hz , reset );
42 divide_10 d2 ( clk_100hz , clk_1000hz , reset );
43 divide_10 d1 ( clk_10hz , clk_100hz , reset );
44 divide_10 d0 ( clk_1hz , clk_10hz , reset );
45
46 endmodule
1 module divide_50 ( outro , new_clk , new_reset );
2 input new_clk , new_reset ;
3 output reg outro ;
4 reg [ 4 : 0 ] counter ;
5 always @ ( posedge new_clk or posedge new_reset )
6 begin
7 if ( new_reset )
8 begin
9 outro <= 1 'b0 ;
10 counter <= 5 'b00000 ;
11 end
12 else if ( counter < 24 )
13 begin
14 counter <= counter + 1 'b1 ;
15 end
16 else
17 begin
18 counter <= 5 'b00000 ;
19 outro <= ~ outro ;
20 end
21 end
22 endmodule
1 module divide_10 ( outro2 , new_clk , new_reset );
2 input new_clk , new_reset ;
3 output reg outro2 ;
4 reg [ 2 : 0 ] counter ;
5 always @ ( posedge new_clk or posedge new_reset )
6 begin
7 if ( new_reset )
8 begin
9 outro2 <= 1 'b0 ;
10 counter <= 3 'b000 ;
11 end
12 else if ( counter < 4 )
13 begin
14 counter <= counter + 1 'b1 ;
15 end
16 else
17 begin
18 counter <= 3 'b000 ;
19 outro2 <= ~ outro2 ;
20 end
21 end
22
23 endmodule
1 module output_result ( out , new_val , clk );
2 output reg [ 7 : 0 ] out ;
3 input [ 2 : 0 ] new_val ;
4 input clk ;
5
6 always @ ( posedge clk )
7 begin
8 out = out + new_val ;
9 if ( out > 99 )
10 out = 8 'b00000000 ;
11 end
12
13
14 endmodule
My pin config isbelow 1 NET "enable" LOC = "G18" ;
2 NET "enable" LOC = CLOCK_DEDICATED_ROUTE = FALSE ;
3 NET "clk" LOC = "B8" ;
4 NET "reset" LOC = "H13" ;
5
6 NET "display[0]" LOC = "L18" ;
7 NET "display[1]" LOC = "F18" ;
8 NET "display[2]" LOC = "D17" ;
9 NET "display[3]" LOC = "D16" ;
10 NET "display[4]" LOC = "G14" ;
11 NET "display[5]" LOC = "J17" ;
12 NET "display[6]" LOC = "H14" ;
13
14 NET "bits[3]" LOC = "F17" ;
15 NET "bits[2]" LOC = "H17" ;
16 NET "bits[1]" LOC = "C18" ;
17 NET "bits[0]" LOC = "F15" ;
von
Alexx (Guest)
2015-12-10 21:37
You can solve your Task using a finite state machine!
I´m just learning VHDL so i cant help u with ur verilog code, but this
task should be realy easy with a state machine. You youst need 5 red
states, 3 yellow, 1 green and start at the begibnning, im sure if u
google it you will find some examples!
von
Joe Joe (Guest)
2015-12-10 22:23
I did google it but its just my teacher never went over verilog than
gave us this project on it. But thats a good idea Ill start on that I
also don't know whats wrong with my seven seg code
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