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Forum: FPGA, VHDL & Verilog Re: Verilog project


von Joe Joe (Guest)


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Hello All I have multiple questions for a project for school I am 
currently using the Nexys 2 board I have to create a traffic light 
controller. I was wondering about a few things that my teacher did not 
go over.
The first one is: How do you make multiple LEDs blink such that it would 
repeat in a traffic light simulation such as 5 seconds red, 3 seconds 
yellow, 1 second green.

My second question is how do you get a countdown to be displayed on the 
seven segment display on a Nexys 2 board?

my third question is how do you use the enable line in the program?

This is the code I have so far
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// Joseph Abel
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// display same as Y
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// bits  same as L 
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module Top_Mod(clk,enable,reset,display,bits);
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  input clk,reset,enable;
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  output [6:0] display;
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  output[3:0] bits;
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  wire[2:0] num;
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  wire[7:0]output_val;
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  wire[3:0] sev;
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  wire[6:0] display_val;
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  wire clock;
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  output_result O2(output_val,num,clock);
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  multiplexing M3(sev,bits,clock,output_val[7:4],output_val[3:0]);
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  Seven_segment S4(display_val, sev);
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  clockslow C5(clk,clock,reset);
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  assign display= display_val;
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endmodule
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module multiplexing(seg, light, clock, M ,L);
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    input clock;
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    input [3:0] M;
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    input [3:0] L;
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    output reg [3:0] seg;
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    output reg[3:0] light;
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    reg select;
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    always @(clock)// generates a signal that performs multiplexing 
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      begin
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      select=~clock;
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      end
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      always @(clock)
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        case(select) // display MSB when select=0
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      0:
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      begin 
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            select =M;
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            light=4'b1110; 
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        end
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      1: 
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      begin
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        select=L;
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        light= 4'b1101;
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      end 
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      endcase
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endmodule

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module Seven_segment(seven,val);
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  input [3:0] val;
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  output reg[6:0] seven;
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    always @(val)
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    begin
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          case(val)
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          0  : seven= 7'b1000000;
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          1  : seven= 7'b1111001;
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          2  : seven= 7'b0100100;
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          3  : seven= 7'b0110000;
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          4  : seven= 7'b0011001;
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          5  : seven= 7'b0010010;
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          6  : seven= 7'b0000010;
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          7  : seven= 7'b1111000;
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          8  : seven= 7'b0000000;
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          9  : seven= 7'b0011000;
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          default : seven=7'b1000000;
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        endcase
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      end
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endmodule
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[\vhdl]
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[vhdl]
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module clockslow(clk, clkreturn,reset);
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input clk,reset;
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output clkreturn;
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wire clk_50Mhz;
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wire clk_100000hz;
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wire clk_10000hz;
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wire clk_1000hz;
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wire clk_100hz;
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wire clk_10hz;
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wire clk_1hz;
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assign clkreturn= clk_1hz;
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divide_50 d6(clk_50Mhz,clk,reset);
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divide_10 d5(clk_100000hz,clk_50Mhz,reset);
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divide_10 d4(clk_10000hz,clk_1000000hz,reset);
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divide_10 d3(clk_1000hz,clk_10000hz,reset);
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divide_10 d2(clk_100hz,clk_1000hz,reset);
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divide_10 d1(clk_10hz,clk_100hz,reset);
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divide_10 d0(clk_1hz,clk_10hz,reset);
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endmodule
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module divide_50(outro, new_clk,new_reset );
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  input new_clk, new_reset;
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  output reg outro;
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    reg[4:0] counter;
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      always @(posedge new_clk or posedge new_reset)
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        begin
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          if(new_reset)
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            begin
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              outro<= 1'b0;
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              counter<= 5'b00000;
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            end
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          else if(counter <24)
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          begin
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            counter <=counter+1'b1;
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          end
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        else
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          begin
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            counter<=5'b00000;
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            outro<=~outro;
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          end
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        end
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endmodule
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module divide_10(outro2,new_clk,new_reset);
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  input new_clk,new_reset;
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  output reg outro2;
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  reg[2:0] counter;
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    always@(posedge new_clk or posedge new_reset)
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      begin
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        if(new_reset)
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          begin
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            outro2<=1'b0;
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            counter <=3'b000;
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          end
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        else if(counter<4)
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          begin
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            counter <= counter+ 1'b1;
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          end
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        else
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          begin
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            counter <=3'b000;
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            outro2<=~outro2;
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          end
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        end
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endmodule
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module output_result(out,new_val,clk);
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    output reg[7:0]out;
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   input [2:0] new_val;
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   input clk;
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   always@(posedge clk)
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    begin 
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      out=out+new_val;
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      if(out>99)
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        out= 8'b00000000;
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      end
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endmodule

My pin config isbelow
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NET"enable" LOC= "G18";
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NET"enable" LOC= CLOCK_DEDICATED_ROUTE=FALSE;
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NET "clk" LOC= "B8";
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NET "reset" LOC= "H13";
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NET "display[0]" LOC = "L18";
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NET "display[1]" LOC = "F18";
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NET "display[2]" LOC = "D17";
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NET "display[3]" LOC = "D16";
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NET "display[4]" LOC = "G14";
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NET "display[5]" LOC = "J17";
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NET "display[6]" LOC = "H14";
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NET "bits[3]" LOC = "F17";
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NET "bits[2]" LOC = "H17";
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NET "bits[1]" LOC = "C18";
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NET "bits[0]" LOC = "F15";

von Alexx (Guest)


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You can solve your Task using a finite state machine!
I´m just learning VHDL so i cant help u with ur verilog code, but this 
task should be realy easy with a state machine. You youst need 5 red 
states, 3 yellow, 1 green and start at the begibnning, im sure if u 
google it you will find some examples!

von Joe Joe (Guest)


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I did google it but its just my teacher never went over verilog than 
gave us this project on it. But thats a good idea Ill start on that I 
also don't know whats wrong with my seven seg code

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