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Subject Author Replies Last post
ADC/DAC Spartan 3E VHDL code problem Irati 4
Makefile does not complete (Linux) Thierry Renaux 5
Implementing Recast block in FPGA. Japa 1
transistor tester Antonio 3
send UDP packets from FPGA meleneemil 15
Need ideas for implementing torque pid control Marcel Meyer 1
ERROR:HDLCompiler:1440 : Non-constant loop condition not supported for for TienNguyen 2
Is ENTRY(_Reset) redundant here? Splee Splee 1
UCF Motor Stepper On FPGA SPARTAn 3E with Driver L 293 Freddy Silaban 12
Excess 3 to gray code using verilog Kamal 0
[Solved] STM32F0 Discovery Board: Connect faild, check config and cable connection Markus J. 6
Use of rotary encoder in Spartan 3E Nirav Bhatt 2
AVR Mega328 does not exit the test mode Dimitris Karatzas 1
RTL technique about "for" combine murakami 1
LVDS Controller LCD Panel nairolf_sch 2
Use I2C Core on DE0? Mo 1
introducing my project "kicksurfer" Frank 16
qsys and user design mike 2
Assignment under elsif does not work Burak Güneş 5
Verilog with FSM Rytis 1
Cortex M0/M0+/M1/M23 BAD Optimisation in GCC Steven Johnson 6
Programmable SoC and SoC FPGA Abdeljalil Bounaime 1
Want to try out GCC 7 (experimental version) on your ARM microcontroller? Freddie Chopin 4
locked Interleaver/deinterleaver VHDL Syed Imam 9
NAND with x input LE DUC LOC 1
Strange problem with a switching regulator Kike 7
Altera ALTCHIP_ID andi6510 0
LUT Questions Abdeljalil Bounaime 13
Simple question about a case statement Luis Gonzalez 1
VHDL project : 5 bit shift reg Michael 42
PS/2 module with LCD Luis Gonzalez 5
If or else if? Which is faster? techno-rogue 8
Vivado warning for RAM component Tudor Ioan 2
output comes after 1.2 sec delay after Power ON Naveedishtiaq Naveed 4
Develop GUI interface for a microcontroller as arduino or similar Erotavlas Erotavlas 1
Error when trying to synthesize Tudor 5
sdram problem in vhdl quartus Vehbi Baycan 2
H-JTAG Error: Can't halt target Amit C. 5
VHDL looping query Ana Ana 1
MM80 RS485 MUX32 multidrop protocol Miros 1
Verilog Simple SPI Code? Ferhat YOL 5
Error (10349): VHDL Association List error at bin_7seg_tester.vhd(13): formal "bin" does not exist Emil 1
Verilog-Range must be bounded by constant expressions Akshay E. 2
Ethernet: No data useful on eth_rxd (Arty Board) Jonas 9
PCB for High Power LEDs Ersin Oezalp 15
Not a homework question, I am 58 1/2! Julian Mortimer 1
Synchronization logic for DAQ IP Viya Vijayan 1
effitient code nick 7
STM32 Changing PWM Duty Cycle in interrupt handler André Van Schoubroeck 7
Programmable controller for ws2813 led Daisy Xu 1
VHDL error “Process clocking is too complex.” Rocking Sharma 3