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Subject Author Replies Last post
Clock domain crossing Stefania M. 7
VHDL Blinking leds James H. 2
gps nmea design using verilog Dammrr R. 11
LCD replacement for GM328a Javier G. 5
counter with signal enable (active high) and synchronous reset signal (active high) Juan 2
adc with fpga interface niclas 8
DS1307 SQWO wrong frequency Kristian S. 2
PCB w/ ESP8266 NodeMCU - Multiple SPI modules not working Ed S. 10
Switching Power Adapter If G. 3
Error loading design (Modelsim student version) Keltuzad 54
Audio codec, weird helicopter sound, potential data error. (WM8731) botoxparty 0
Battery Charging Circuit (2A) If G. 2
Double Data Rate Serializer verilog Atalin 3
simbol moving using buttons cataru 1
Abel to VHDL Jose 3
RFID 125kHZ HTRC110 & PIC Slash M. 2
Image processing in Verilog - simulation yk_learner 2
help in reading a large text file using verilog. Alangs Kannan 17
RaspberryPi 3 with NFC for scanning mobile phone Ephaltes 2
R Shiny: Creating factor variables and defining levels Tobi M. 0
Arduino code not able to upload twice Caroline Hein 4
Set callback to validate a server certificate // security protocol used in a HTTP GET request Sam 0
is it possible for bcd to ascii module? John B. 7
Problem when building Brownout Detector Xiangyu C. 0
for loop in verilog code nelson george 20
Battery protection unit VV V. 5
What is 3W Rule of PCB design? Lernend B. 3
Verilog: # Error loading design Vasily D. 1
DC-DC-Boost-Converter x3oo 12
Project announcement: EBlink free debug tool for STlinkV2/3 Gerard Z. 0
Can anyone help me to solve this verilog(beginner) question or suggest me any source for solving Omar K. 1
IoT Hackathon - Integrate Everything with IOTA DANIEL D. 2
Battery Management System Design Moi 10
beginner question on gate level d flip flop simulation Jimmy Z. 1
BT module RRD-305 (QCC 3005): any config info? Josef 0
ice40HX8k enable signal from clock Fabian 1
How to properly multiply signed and unsigned signed unsigned 1
AVR clock prescaler (CLKPR) and gcc code optimization Peter-Jan Peters 13
Synthesis: Mix of sync and async assignments to register if else what when 5
Microcontroller ally 1
Determining trace delay for input delay constraints Timing violation 13
SN74AHC 14 - LTspice Setup DoKfROG 4
Hardware-independent µC core? Matthias U. 5
Transistor tester program error Cafeee S. 1
Voltage drop consequences in led strips fuberator 2
Enhanced Tiger Single Board Computer Myron P. 3
Opamp in an audio circuit Luca 20
Getting to the Root Cause of BGA Assembly Problems smartronics 1
How powerful is Verilog at using parameters to specify designs? Kevin S. 0
Quiet servo Motors with high Torque Lukas Schmidt-Wiegand 3
How to read unknown SPI flash? ATm 0