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Subject Author Replies Last post
High speed FPGA design Silver 2
Printf, putc, and getc serial issues Rick Mc 1
Need help with Verilog project idea Amin 1
Altera Cyclone 3/4 DDR2 Sample Design [emi_ddr2_ciii.zip] Antony Mathew 3
VHDL process issue : double execution Sacha 17
Network on chip implementation in FPGA Bala Krishnan 2
Verilog state machine query Kenny Millar 9
DE0_NANO_ADC jeorges FrenchRivera 4
function "to_integer" Mira Miyou 9
Digital to analog converter DAC and FPGA issam sassi 0
Drive 12V 15A load with PWM 18V-48V 2A Saif Butt 0
Progam in VHDL for a ttl finder Jose Maria 0
Processing/Sampling IF(IQ) signals Himadri 1
Verilog FPGA Compatibility Charan Mehta 2
Amontec out of order? markushh 1
32-to-1 multiplexer VHDL code simplification Zoltan Preiner 2
RF class AB power amp my 1
4-Bit Structural Adder using port map Jay JA 4
VHDL Counter Problem (Please help) Icy Snow 2
warning when synthesis afsoon 2
Error when using with-select-when in VHDL Ayush Khemka 3
Parallel MAC unit based on modified booth algorithm Jithin Smmb 1
VHDL MODEL FOR SINGLE D-TYPE LATCH WITH 3-STATE OUTPUT Naija Coding 3
modified nodal analysis Mohammad Mothermohammad 2
Basic memory unit help Omar Rashad 2
USB interface Lukas 1e+007 8
Simple 16 bit Arithmetic Unit Omar Rashad 3
Xilinx 8.1 & Xilinx 14.7 Version will not compile my design Lewis Mbuthia 3
FPGA # Processor Itron Xtron 3
16 bit PISO register Omar Rashad 18
Newbie question about 'inout' Kenny Millar 7
Two digit BCD adder Yhx Yhx 2
locked 16 bit serial multiplier Omar 13
FAT fs robustness and consistency check Aldo Dolfi 2
multiplier a matrice Mohammad Mothermohammad 3
Linking two files with 2 mains using objcopy Opt Em 1
mux using system generator REKHA V P 2
L3G4200D Gyro rotation angle Fin Wood 2
accurate counter Mohammad Mothermohammad 3
Choice of Hardware Sunayana C. 0
Controller Chip for Thermal Printer (like Matsushita EPL1604T2 or EPL1801S2E) Christian Guenther 0
ATMEGA 644 on Pollin NETIO: sei leads to reset/restart Michael Haussmann 1
locked VHDL code help (beginner level) Omar 6
MACHXO2 - accessing Wishbone EFB i2c from Verilog? Kenny Millar 6
NXP Flash access time Sweety Water 1
Using the Xilinx ISE Design Suite 14.7 version Juan 6
RS-232 communication with XUPV5-LX110T evaluation platform (Xilinx) issam sassi 0
Audio Interfacing with FPGA Jack Born 12
Algorithm for x/63 and x/127 Nikolaos Kavvadias 13
Binning + Pipeline, How to do it, please? Enrique Perez 7
Display 640x480 Nexys 3 board sketchy 8