I plan a project with the LPC1788. It has internal flash (512k) and SRAM (64k). Does anybody knows the access time for flash and for SRAM access? Is code executed in flash (XIP) as fast as code that is executed in SRAM? The code size might exceed the internal RAM size. If XIP is slower than run in RAM and the code does not fit in internal SRAM I would have to consider external RAM additionaly. What is your experience?
No experience, but have a look at http://www.lpcware.com/content/faq/lpcxpresso/placing-specific-functions-ram-blocks. There can't be a general rule because of the pipeline, the individual code executed and so on. In the UM there is some information about clockrate, waitstates and so on. The LPCOpen forum is the right place to go on.