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Subject Author Replies Last post
looking for an LED in 3528 package with WS2811 or similar controller Chris 0
Installing gcc 4.9 in ARMv7 Jyothi K. 0
Open Source VHDL Verification Methodology(OSVVM) SparkyT 1
VHDL Audio Codec Kody Haugli 3
Interfacing an FMC CARD and FPGA JSF 2
Open Source ZigBee Simos Vassiliadis 0
VHDL coding Question Michael 16
Regarding parallel to serial converter Basavaraj H. 0
Text output for FPGA REKHA V P 3
Function application Mahdi 3
help with a vhdl calculator Yair Orta 1
Possible wrong explanation on "STM Discovery as Black Magic Probe" page Zsolt Gaspar 1
Traffic Light VHDL , counter Gabriel 1
analyse the ATXMEGA128A1 calculation speed Xinyu Shu 1
Interfacing AD7655 with FPGA jeorges FrenchRivera 2
State Machine for SPI Master/Slave Interface Nayan Patel 8
HELP VHDL code for pipeline multiplier Blood Eagle 2
Alternative to OpenCL vnguyen 0
VERILOG CODE Akshay E. 4
STM32F4 PWM outputs do not have the same frequency after updated Minh Pham 1
Vhdl on FPGA, need to understand a syntax Hakon Veddegjerde 3
Kintex UltraScale with two DDR4 interafces? Oren Hoffmann 0
analogue-to-digital decoder hossam 4
Entering a Cyclone1 With a 100MHz ADC ASSOUKE Jean 1
frequency doubling with a ring mixer oscillator 6
I have this problem when I simulated it. Lan100 Lan100 6
Simulation Step by step (simulation pas à pas) Hicham Amine 6
Verilog Loop operation with registers. Eldar Ismailov 0
GPIO Ports on Keil MCB1800 with LPC1857 andreas_mue 0
part of a reg as statmeant in case shmulik 6
locked Reading .txt file and putting information in RAM Renato Pereira 4
vhdl code for si4136 Saman Saman 2
Multi-source error Javier PA 4
FPGA: i get a different answer in modelsim and in device Amine Amine 1
FPGA: Artix 7 VS Virtex 5 Amine Amine 2
locked [HOW TO] Interface an SD XC 64GB Card Class 10 Brian 5
Large arrays Saltwater 4
LED intensity Oer Pdw 5
Learning VHDL beyond basics Johan 1
IEEE 1800 SystemVerilog LRM Jack 1
help regarding UART Xilinx IP Ananya Devraj 4
STM32F4 IMPRECISERR, trouble debugging SGT Jacobs 5
Multi Cycle VHDL Code Cemal Unal 3
generate random bit function Mike 1
Counter Design with D Flip-Flop Cemal Unal 3
Generalize the module in verilog Muhammad Awais 1
Heraeus Kulzer Unixs PIC16C71-04/P Ciprian Gliguta 2
synthesis translate_off / on Faras 1
How to generate one pulse from a button OnePulse 2
Program size explodes when using the "new" operator ARTHUR W. 4
Fusebyte to program with PonyProg cobramostar 3