Hello, I am doing a project for one of my 4th year classes for Electrical Engineering which is based around active noise cancelation. I have a Digilent ZYBO Zynq 7000 Development Board and run the Vivado program. Our board has a mic in port and a headphone out port and what I am trying to do is build a codec for an incoming noise signal although I am having some trouble starting out. I have came across some example IP block diagrams from the Digilent website that deals with audio and video codec, but I can't seem to access the VHDL code. I was wondering if anyone would have some information on where I could find some good starting tips/code for an audio codec? As well I was wondering if anyone is familiar with Vivado and System Generator and could explain how System Generator generates IP from simulink block diagrams. Thank you.
forget it simulink and system generator is a world which requires about two years to learn about and vivado is also not self explaining. you are running in too large steps - why don't you start with the maths and algorithms behind noise cancelling? an audio codev in vhdl is not required in any way, since this should be done in hardware. you only need some configuration of the codec and an input output system with your code in between.
You need to read: http://www.analog.com/media/en/technical-documentation/data-sheets/SSM2603.pdf and page 23 of http://www.digilentinc.com/data/products/zybo/zybo_rm_b_v6.pdf The audio codec itself has an DSP inside. You have to configure the Codec so you get audio data in the FPGA. You have to implement a I2S or I2C statemachine.
You should start with simple tasks as freelancer suggested. The first thing you may try is to output something on the "headphone out" port. Then you may try to sample the input coming over the MIC port. Then you may try to speak on the MIC and output it on the HEADPHONE port. This sounds simple but you still require to generate/extend your design. Basics such as clock generation and synchronizing all the stuff and so on are things which you need to take care of. Once you have the pipeline MIC_IN -> FPGA -> HEADPHONE_OUT it will be much easier for you to add a processing module to it. Regards