Oer Pdw wrote:
> I got some code but I don't think it's good.
You are right. This will work in a simulator at best. But you will never 
ever get it on hardware.

The major drawback is the missing clock inside the process. It is not 
enough to have the clock in the sensitivity list. Look how all the 
others do it...

The problem is that everyone has different task so I can't check
Can you help me?

Oer Pdw wrote:
> The problem is that everyone has different task
What should this sentence say?

What I said is: there is no clock in your design! But each counter needs 
a clock because its built of flipflops. Have a look how everybody on the 
world describes a counter. There must be a rising_edge() or a 'event 
in your code!

Is it good now?

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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.numeric_std.all;

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entity PWM is

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  generic

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  (

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    sd        : unsigned(7 downto 0) := X"C3" -- 195 in hex

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  );

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  port

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  (

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    clock     : in   std_logic;

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    switches  : in   unsigned(7 downto 0);

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    pwm       : out  std_logic

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  );

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end PWM;

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architecture behave_PWM of PWM is

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  signal counter : unsigned(15 downto 0);

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begin -- architecture

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  pwm_proc: process (clock)

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  begin

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if(clock'event and clock='0'") then

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    if (counter <= switches*sd) then

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      pwm <= '1';

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    else

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      pwm <= '0';

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    end if;

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    if (counter >= 50000) then

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      counter <= (others => '0');

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    else

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      counter <= counter + 1;

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end if;

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    end if;

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  end process;

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end behave_PWM;

Oer Pdw wrote:
> Is it good now?
There is a syntax error in it, but the concept is ok.

> Is it good now?
Take a little test bench and check it out...