Vhdl on FPGA, need to understand a syntax

Hi!

I'm working on getting a single cycle arm processor to work on a FPGA 
chip.
but I have a problem with just one line to get it work.

I'm a beginner in vhdl and I'm just putting together prewritten 
code(from school).

here is my problem:

Y:  std_logic
A:  std_logic_vector(3 downto 0)
B:  std_logic
C:  std_logic

Y <= ((and A) and B) or C;

I dont understand what I'm anding A with. If I can get an understanding 
of the line, i can write a equivalent code to get it to work.

-Håkon