State Machine for SPI Master/Slave Interface

Nayan P. OP #4004456
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Dear all,

I am trying to write a state machine that checks to see if correct data 
is being received on the SPI link by lighting an LED.

I have written a code but I am not sure if I am writing the state 
machine correctly, it definitely does not compile.

Here is the code that I have written in relation to the test bench, 
please find the file attached.


1
library IEEE; -- Reference for VHDL source code  

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use IEEE.STD_LOGIC_1164.all; -- Package defined in the IEEE (Found in library IEEE)

3


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-- Entity declaration

5
entity spi_statemachine is

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   generic (n: positive := 16; -- Number of bits

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  port (-- Master --                        

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      di_m: in std_logic_vector(15 downto 0);

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      wren_m: in std_logic;

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      -- Slave --

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      do_s: out std_logic_vector(15 downto 0);

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      do_valid_s: out std_logic;

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      -- Clock operation --

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      rst_i: in std_logic;

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      clk_i: in std_logic;

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      -- Output detection --

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      correct: out std_logic);

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end spi_statemachine;

19


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-- Architecture behaviour

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architecture detect of spi_statemachine is

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type state_type is (createData, writeData, delay, writeEnable,

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              checkValid, receivedData, checkFinished);  -- Enumeration type

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signal state: state_type;

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begin

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  P1: process (clk_i, rst_i) -- Clock and reset

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  variable dataLength: integer := n; -- Length of data

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  variable count: integer := 1;

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  begin

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    if rst_i = '0' then -- Reset operation used initialize all signals to predetermined state

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      state <= createData; 

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    elsif clk_i'event and clk_i = '1' then  -- Signal attribute used to test for a change on a signal

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      case state is

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        when createData =>

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            state <= writeData;

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          else

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            state <= createData;

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          end if;

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        when writeData =>

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            di_m <= std_logic_vector(to_unsigned(dataLength,n)); -- Write data

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            state <= delay;

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        when delay =>

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            count := count + 1;

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          if (count > 1) then

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            state <= writeEnable;

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          count := 0;

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          else

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            state <= delay;

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          end if;

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        when writeEnable =>

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          wren_m <= '1';

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          state <= checkValid;

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        when checkValid =>

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          wren_m <= '0';

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          state <= receivedData;

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        when receivedData =>

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          if do_s = di_m then

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            state <= checkFinished;

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          end if;

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        when checkFinished =>

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          correct <= '1';

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        when others => null;

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      end case;

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    end if;

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  end process;

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end detect;


Any kind of help will be appreciated.

Kind regards,

Nay
Attached files:
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Lothar M. Moderator (Company: Titel) #4005600
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Nayan Patel wrote:
> How do I declare an output from the slave component to the code that I
> am writing above?
What slave?

> it definitely does not compile.
But you get no warnings or error messages?

> Here is the code that I have written in relation to the test bench
So the waveform picture is what your code should do after being 
completed? Where's the testbench for that waveform?
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Nayan P. OP #4006422
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Lothar Miller wrote:
> Nayan Patel wrote:
>> How do I declare an output from the slave component to the code that I
>> am writing above?
> What slave?
>
>> it definitely does not compile.
> But you get no warnings or error messages?
>
>> Here is the code that I have written in relation to the test bench
> So the waveform picture is what your code should do after being
> completed? Where's the testbench for that waveform?

I am using a master block to send data to the slave block and the state 
machine block will check to see if the correct data is received.

I get the following error message:

1
Error (10482): VHDL error at spi_statemachine.vhd(70): object "do_o" is used but not declared


I am trying to assign the output 'do_o' of the slave block to the input 
'di_m' of my state machine block.

Please find the file of the test bench attached.

Kind regards,

Nayan
Attached files:
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Lothar M. Moderator (Company: Titel) #4006447
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Nayan Patel wrote:
> Please find the file of the test bench attached.
This here could be cut down several lines:
1
-- Clock generator (50% duty cycle)

2
  -- Master clock --

3
  -- Serial clock --

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  clk_process_serial: process        -- Identifying the process

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  begin                        -- Begin process

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       sclk_i <= '0';              -- Serial clock signal is '0'.

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       wait for clk_period/2;          -- Serial clock signal is '0' for 5ns

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       sclk_i <= '1';              -- Serial click signal is '1'

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       wait for clk_period/2;          -- Serial clock signal is '1' after 10ns

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  end process clk_process_serial;      -- End process

11
  

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  -- Parallel clock --

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  clk_process_parallel: process        -- Identifying the process

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  begin                        -- Begin process

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       pclk_i <= '0';              -- Slave clock signal is '0'.

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       wait for clk_period/2;          -- Slave clock signal is '0' for 5ns

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       pclk_i <= '1';              -- Slave clock signal is '1'

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       wait for clk_period/2;          -- Slave clock signal is '1' after 10ns

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  end process clk_process_parallel;    -- End process

20
  

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  -- Slave clock --

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    clk_process_slave: process        -- Identifying the process

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  begin                        -- Begin process

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       clk_i <= '0';                -- Slave clock signal is '0'.

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       wait for clk_period/2;          -- Slave clock signal is '0' for 5ns

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       clk_i <= '1';                -- Slave clock signal is '1'

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       wait for clk_period/2;          -- Slave clock signal is '1' after 10ns

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  end process clk_process_slave;      -- End process

Just by this here:
1
-- Clock generator (50% duty cycle)

2
  clk_i  <= not clk_i after clk_period/2; 

3
  sclk_i <= clk_i;

4
  pclk_i <= clk_i;


Nayan Patel wrote:
> I get the following error message:
I cannot find do_o in any of the VHDL code you provided. Is it hidden 
somewhere else?

And of course, this here won't work at all:
1
      :

2
      do_s: out std_logic_vector(15 downto 0);

3
      :

4
      :

5
          if do_s = di_m then    -- it is not allowed to read an output port!

6
      :

In VHDL a output cannot be read.
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Nayan P. OP #4006510
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Lothar Miller wrote:
> Nayan Patel wrote:
>> I get the following error message:
> I cannot find do_o in any of the VHDL code you provided. Is it hidden
> somewhere else?

The output 'do_o' is read from the slave block, please find the file of 
the master block and slave block attached.

Kind regards,

Nayan
Attached files:
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Nayan P. OP #4006579
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Lothar Miller wrote:
> And where is the file with the line of code causing the errror:
> spi_statemachine.vhd(70)
>
> Heck, it is so exhausting to worm every small bit of information out of
> someone...  :-/

Apologies for the confusion, please find state machine file attached.

I have also attached the wrapper (Top-level entity) for the 'spi_master' 
and 'spi_slave' cores, to synthesize the 2 cores and test them in the 
simulator.

Kind regards,

Nayan
Attached files:
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