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Forum: FPGA, VHDL & Verilog Simulation Step by step (simulation pas à pas)


von Hicham A. (Company: Morocco Technologies) (hicham1959)


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Hi, Hope you are doing well.
I'm looking for some informations about what we call "Simulation Step by 
step" in Modelsim, what is the intented/advantages of this simulation?
If there is some documents, exercices, projects about this topic, i will 
be very grateful.
Thank's for your time :)

von Lothar M. (lkmiller) (Moderator)


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Hicham Amine wrote:
> what we call "Simulation Step by step"
How is this functionality called in common?
Is it "Single-Step"?
Then (to speak for VHDL) the only use is to debug a 
process/function/procedure with variables and loops inside. Then you can 
have a look for intermediate values...

von Hicham A. (Company: Morocco Technologies) (hicham1959)


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Thank you Lothar Miller, well it's for VHDL, FPGA Test and Vereficiation 
domain

von Lattice User (Guest)


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Hicham Amine wrote:
> Thank you Lothar Miller, well it's for VHDL, FPGA Test and Vereficiation
> domain

That doesn't answer his question.

Where did the phrase "Simulation Step by step" come from?
For me it sounds it is from some kind of tutorial.

von Hicham A. (Company: Morocco Technologies) (hicham1959)


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Hi Lattice,
Simulation Step by step (= simulation pas à pas in french), it's a debug 
method used for debuggin the simulation environnement (work bench), it 
help to segment the debug into block by block... to see the origin of 
the FAIL/Bug(is that come from RTL code/ or it's a Benche coding error).
That what i know as a few information, now im looking for a tutorial or 
a training that contain this kind of simulation.
Thank's

von René D. (Company: www.dossmatik.de) (dose)


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If yuo habe found a good introduction for modelsim, please post a link.

I had started sometimes with modelsim, but I fall back to GHDL.

This is also VHDL simulator.

von Duke Scarring (Guest)


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René D. wrote:
> introduction for modelsim
vcom *.vhd
vsim -gui testbench

add wave *
run -all
That's it ;-)

Duke

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