Hi
Who can help me please.
I want to make some loop operation. for example: use loop in register 
indexes

reg [7:0] res;
reg [7:0] buff
for (i = 0; i < 8 ; i = i + 1)
res <= buff[i+1:i] + i;
------------------------------------------
module integers( clock, res
    );
input clock;
output res;
wire clock;
reg [7:0] res;
reg [7:0] buff = 0;
genvar i;

  for (i = 0; i < 8 ; i = i + 1)
  begin
  always@ (negedge clock)
    begin
      res <= buff + i;
          end
  end
---------------------------------
it outputs only one. but should counts.