Forum: FPGA, VHDL & Verilog Verilog Loop operation with registers.

von Eldar I. (Company: Optimal Dynamics) (ismailov-e)

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Who can help me please.
I want to make some loop operation. for example: use loop in register 

reg [7:0] res;
reg [7:0] buff
for (i = 0; i < 8 ; i = i + 1)
res <= buff[i+1:i] + i;
module integers( clock, res
input clock;
output res;
wire clock;
reg [7:0] res;
reg [7:0] buff = 0;
genvar i;

  for (i = 0; i < 8 ; i = i + 1)
  always@ (negedge clock)
      res <= buff + i;
it outputs only one. but should counts.


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