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Forum: FPGA, VHDL & Verilog I have this problem when I simulated it.


von Lan100 L. (lan100)


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Hi everybody,
I don't understand this problem:


S1 is concurrent.

signal s1: std_logic_vector(7 downto 0):="10101010";
constant c1: std_logic_vector(7 downto 0):="10101010";

When i make this assignation:   s1(7 downto 1)<= s1(6 downto 0);


In the Modelsim tool, I have shown S1 <="00000000";  instead of 
s1<="01010100"

Why?

Thank you for your assitance.

von Lothar M. (lkmiller) (Moderator)


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Lan100 Lan100 wrote:
> Why?
Don't know it. The actual problem is outside the posted code snippet...

Post more code.
Post what you expect.
And how you see that it don't do what you expect.

von lan100 (Guest)


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Hi,

I make this code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity CONcurrence is
end CONcurrence;

architecture data of CONcurrence is

signal s1: std_logic_vector(7 downto 0):="10101010";
constant c1: std_logic_vector(7 downto 0):="10101010";

begin

s1(7 downto 1)<= s1(6 downto 0);

end Behavioral;


Best Regards.

von uwe (Guest)


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>begin
>s1(7 downto 1)<= s1(6 downto 0);
>end Behavioral;

Without clock?! You should draw it with FlipFlops. Try it!

von lan100 (Guest)


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It works but i don't want the behavioral style but by dataflow style.

von Tschaebe (Guest)


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lan100 wrote:

do you really mean
> begin
>
> s1(7 downto 1)<= s1(6 downto 0);
>
> end Behavioral;

or should it be
begin
   s1(7 downto 1)<= c1(6 downto 0);
end Behavioral;

(note the constant c1 here). In your case you are forming a 
combinatorial loop...

Tschaebe

von Lothar M. (lkmiller) (Moderator)


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lan100 wrote:
> It works but i don't want the behavioral style but by dataflow style.
Sounds like bullshit bingo. The only thing you have there is a 
combinational loop. It makes no sense on real hardware.

And for simulation: just draw it yourself on a sheet of paper. After 7 
iterations of this assignment there's no additional change and you have 
what you get...

Edit: too slow... ;-)

: Edited by Moderator

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