EmbDev.net

Forum: FPGA, VHDL & Verilog Entering a Cyclone1 With a 100MHz ADC


Entering a Cyclone1 With a 100MHz ADC
von ASSOUKE J. (dro)

Rate this post
• ▲ useful
▼ not useful 
Hi everyone,;
 I am currently writting  VHDL program to process datas acquired at 
100Mhz.
But first of all i am afraid of something:
   the fact that my fpga is old (cyclone 1) and that i work with a high 
speed adc scares me, since my adc card transfers data to my FPGA  in a 
parallel communication (at one clock). So i think that it is possible 
that my Fpga does't see corectly all the bits transferred from the ADC.
   I need to know if there is a care which should be taken while writing 
the VHDL code regarding this (for exemple is it necessary to do a Clock 
cross domain , or a buffer or something like that).
  If there is a thing that you don't get well,please feel free to ask 
me.

Thank you .

Report post Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Quote selected text Reply Reply with quote
Re: Entering a Cyclone1 With a 100MHz ADC
von Sigi (Guest)

Rate this post
• ▲ useful
▼ not useful 
100MHz with CycloneI is not a problem (200MHz ADCs are possible),
if there are timing problems, just use IO-FFs/Registers or split
the e.g. 8Bit-ADC-100MHz-Data into 16Bit-50MHz-Data.

Report post Edit Delete Quote selected text Reply Reply with quote
Watch this topic | Disable multi-page view
Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.