I am currently writting VHDL program to process datas acquired at
But first of all i am afraid of something:
the fact that my fpga is old (cyclone 1) and that i work with a high
speed adc scares me, since my adc card transfers data to my FPGA in a
parallel communication (at one clock). So i think that it is possible
that my Fpga does't see corectly all the bits transferred from the ADC.
I need to know if there is a care which should be taken while writing
the VHDL code regarding this (for exemple is it necessary to do a Clock
cross domain , or a buffer or something like that).
If there is a thing that you don't get well,please feel free to ask
Thank you .