Forum: FPGA, VHDL & Verilog Interfacing AD7655 with FPGA

von jeorges F. (Company: xlue) (khal1985)

Attached files:

Rate this post
0 useful
not useful
Hi guys,

I'm trying to interface a 16-bit serial ADC to an FPGA cyclone IV. The 
ADC that I'm using is the AD7655 from analog device.

1. Since the ADC is going to be operating in External Clock Data Read
(Previous) During Convert mode(page 22 of
http://www.analog.com/static/imported-files/data_s..., my
input clock needs to be 32 MHz at least(50 MHz in my case).

2. My problem is that the practical timing specification doesn't feed 
the theoretical one. That means for example, in the theory, busy HIGH is 
0.875 maximum µs while in practice I obtain 1.64 µs.(the time 
specifications is on 
http://www.analog.com/static/imported-files/data_sheets/AD7655.pdf, page 

enclosed you find the schematic of the ADC  and the time diagram 
obtained with logic analyzer.

I'd appreciate any help to understand my problems.

Best regards

von that's how (Guest)

Rate this post
1 useful
not useful
Figure 22 shows you how to accomplish 1 MSPS. 1.75us (t7) is used to 
convert channelA and channelB then you'll have 0.25us (t8) to read them. 
=> 2samples/2us = 1MSPS

von jeorges F. (Company: xlue) (khal1985)

Rate this post
0 useful
not useful
OK, thank you very much, now i understand.

best regards


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.