Interfacing AD7655 with FPGA

Hi guys,

I'm trying to interface a 16-bit serial ADC to an FPGA cyclone IV. The 
ADC that I'm using is the AD7655 from analog device.


1. Since the ADC is going to be operating in External Clock Data Read
(Previous) During Convert mode(page 22 of
http://www.analog.com/static/imported-files/data_s..., my
input clock needs to be 32 MHz at least(50 MHz in my case).

2. My problem is that the practical timing specification doesn't feed 
the theoretical one. That means for example, in the theory, busy HIGH is 
0.875 maximum µs while in practice I obtain 1.64 µs.(the time 
specifications is on 
http://www.analog.com/static/imported-files/data_sheets/AD7655.pdf, page 
5).

enclosed you find the schematic of the ADC  and the time diagram 
obtained with logic analyzer.

I'd appreciate any help to understand my problems.

Best regards