VERILOG CODE

Akshay E. wrote:
> but I know its wrong.
Where do you know this from? And WHAT error message do you get in WHICH 
line of WHATEVER code?

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module mhash(clk,in,match);

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input clk;

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input [7:0]in;

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integer i;

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reg [2:0] sum=3'b000;

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output reg match;

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reg [2:0] mem[7:0];

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initial

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begin

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mem[0]=3'b110;

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mem[1]=3'b010;

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mem[2]=3'b111;

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mem[3]=3'b000;

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mem[4]=3'b110;

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mem[5]=3'b101;

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mem[6]=3'b011;

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mem[7]=3'b110;

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end

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always@(posedge clk)

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begin

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for(i=3'd0;i<8;i=i+1)

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begin

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if (in[i]==1'b1)

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sum=sum ^ mem[i];

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end

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$display("Sum=%b %b %b",sum,in,in[7]);

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end

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endmodule

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module tb;a

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reg [7:0]in;

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reg clk;

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wire match;

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initial 

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begin

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clk=0;

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#10 in=101010101;

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end

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always

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#5 clk=~clk;

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initial

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#100 $finish;

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initial 

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begin

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$monitor($time,"\t in=%b",in);

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$dumpfile("my.dmp");

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$dumpvars(0,tb);

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end

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mhash c1(clk,in,match);

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endmodule

This my code..
and my output is

                   0   in=xxxxxxxx
Sum=000 xxxxxxxx x
                  10   in=10110101
Sum=100 10110101 1
Sum=000 10110101 1
Sum=100 10110101 1
Sum=000 10110101 1
Sum=100 10110101 1
Sum=000 10110101 1
Sum=100 10110101 1
Sum=000 10110101 1
Sum=100 10110101 1

The problem is, I gave the value 10101010 to test bench and it shows 
in=10110101. Why?. and I am getting bit by bit values. I am sorry for 
that.

My aim is to 'xor' all the mem[i] values to sum, for every in[i]=1

Akshay E. wrote:
> This my code..
You did not hear anything about "indention" up to now?

> i give 10101010 to test bench
> input [7:0]in;
> in=101010101;
In fact you try to give 9 bits to an 8 bit vector...