EmbDev.net

Forum: FPGA, VHDL & Verilog VERILOG CODE


von Akshay E. (akshay_e)


Rate this post
0 useful
not useful
module mhash(clk,in,match);
input clk;
input [7:0]in;//
integer i;
reg [2:0] sum=3'b000;
output reg match;
reg [2:0] mem[7:0];

If we give the input value 10101010 for 'in', How to access bit by bit? 
I tried with in[0],in[1]...but I know its wrong. Is there any way?

von Lothar M. (lkmiller) (Moderator)


Rate this post
0 useful
not useful
Akshay E. wrote:
> but I know its wrong.
Where do you know this from? And WHAT error message do you get in WHICH 
line of WHATEVER code?

von Akshay E. (akshay_e)


Rate this post
0 useful
not useful
1
module mhash(clk,in,match);
2
input clk;
3
input [7:0]in;
4
integer i;
5
reg [2:0] sum=3'b000;
6
output reg match;
7
reg [2:0] mem[7:0];
8
initial
9
begin
10
mem[0]=3'b110;
11
mem[1]=3'b010;
12
mem[2]=3'b111;
13
mem[3]=3'b000;
14
mem[4]=3'b110;
15
mem[5]=3'b101;
16
mem[6]=3'b011;
17
mem[7]=3'b110;
18
end
19
20
always@(posedge clk)
21
begin
22
23
for(i=3'd0;i<8;i=i+1)
24
begin
25
if (in[i]==1'b1)
26
sum=sum ^ mem[i];
27
end
28
$display("Sum=%b %b %b",sum,in,in[7]);
29
end
30
31
endmodule
32
33
module tb;a
34
reg [7:0]in;
35
reg clk;
36
wire match;
37
initial 
38
begin
39
clk=0;
40
#10 in=101010101;
41
end
42
43
always
44
#5 clk=~clk;
45
46
initial
47
#100 $finish;
48
49
initial 
50
begin
51
$monitor($time,"\t in=%b",in);
52
$dumpfile("my.dmp");
53
$dumpvars(0,tb);
54
end
55
56
mhash c1(clk,in,match);
57
endmodule

This my code..
and my output is

                   0   in=xxxxxxxx
Sum=000 xxxxxxxx x
                  10   in=10110101
Sum=100 10110101 1
Sum=000 10110101 1
Sum=100 10110101 1
Sum=000 10110101 1
Sum=100 10110101 1
Sum=000 10110101 1
Sum=100 10110101 1
Sum=000 10110101 1
Sum=100 10110101 1

The problem is, I gave the value 10101010 to test bench and it shows 
in=10110101. Why?. and I am getting bit by bit values. I am sorry for 
that.

My aim is to 'xor' all the mem[i] values to sum, for every in[i]=1

: Edited by Moderator
von Lothar M. (lkmiller) (Moderator)


Rate this post
0 useful
not useful
Akshay E. wrote:
> This my code..
You did not hear anything about "indention" up to now?

> i give 10101010 to test bench
> input [7:0]in;
> in=101010101;
In fact you try to give 9 bits to an 8 bit vector...

von Tschaebe (Guest)


Rate this post
0 useful
not useful
Akshay E. wrote:
1
> #10 in=101010101;

In verilog, the default base for a number is 10, so 101010101 is 
'd101010101 or 'h6054ab5. Truncate this to 8 bits you will get 
8'b10110101

Akshay E. wrote:
1
> 10   in=10110101

This is what you get, so why are you surprised or sorry :-)?

Maybe you really meant:
1
#10 in= 8'b01010101;

Tschaebe

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.