FPGA: Artix 7 VS Virtex 5

OP #3966622
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I have a VHDL code to implement a arithmetic modular multplier.
my code gets synthesized correctly  without errors,
but with Artix 7 i have 4800 warnings but with Virtex 5 only 700 
warnings

I use ISE 14.

can you please explain me why this difference between this two device ?
thanks

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