Cemal Unal wrote:
> Can someone help me how I can write it ? :)
What comes after the ending '0'?
If the counter loops again from the beginning, then implement a counter
that counts in cycles from 0 to 9 and decode each counter step to your
desired output value afterwards:
reg [3:0] cnt = 4'h0;
always @ (posedge clock)
begin : COUNTER
if (cnt < 9)
cnt <= cnt + 1;
else
cnt = 4'h0;
end
always @ (cnt)
begin : DECODER
case (cnt)
4'h0: out = 4'b0000;
4'h1: out = 4'b0010;
4'h2: out = 4'b0100;
:
4'h9: out = 4'b0011;
endcase
end

And so you don't have to dig around with DFFs and logic gates. The
synthesizer/compiler has to deal with it...