Cemal Unal wrote:
> Can someone help me how I can write it ? :)
What comes after the ending '0'?
If the counter loops again from the beginning, then implement a counter
that counts in cycles from 0 to 9 and decode each counter step to your
desired output value afterwards:
1  reg [3:0] cnt = 4'h0;

2  
3  always @ (posedge clock)

4  begin : COUNTER

5  if (cnt < 9)

6  cnt <= cnt + 1;

7  else

8  cnt = 4'h0;

9  end

10  
11  always @ (cnt)

12  begin : DECODER

13  case (cnt)

14  4'h0: out = 4'b0000;

15  4'h1: out = 4'b0010;

16  4'h2: out = 4'b0100;

17  :

18  4'h9: out = 4'b0011;

19  endcase

20  end

And so you don't have to dig around with DFFs and logic gates. The
synthesizer/compiler has to deal with it...