Counter Design with D Flip-Flop

OP (Company: Hacettepe University) #3943135 
I will write a counter code in verilog that counts like this
(with D Flip Flop and some logic gates)

0000 -> 0
0010 -> 2
0100 -> 4
0110 -> 6
1000 -> 8
1010 -> 10
1100 -> 12
1001 -> 9
0110 -> 6
0011 -> 3
0000 -> 0

Can someone help me how I can write it ?  :) thanks
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Moderator (Company: Titel) 
Cemal Unal wrote:
> Can someone help me how I can write it ?  :)
What comes after the ending '0'?

If the counter loops again from the beginning, then implement a counter 
that counts in cycles from 0 to 9 and decode each counter step to your 
desired output value afterwards:
1
reg [3:0] cnt = 4'h0;

2


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always @ (posedge clock)

4
begin : COUNTER

5
  if (cnt < 9) 

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    cnt <= cnt + 1;

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  else

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    cnt = 4'h0;

9
end

10


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always @ (cnt) 

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begin : DECODER

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  case (cnt)

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    4'h0: out = 4'b0000;

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    4'h1: out = 4'b0010;

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    4'h2: out = 4'b0100;

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    :

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    4'h9: out = 4'b0011;

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  endcase

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end


And so you don't have to dig around with D-FFs and logic gates. The 
synthesizer/compiler has to deal with it...
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Guest 
Lothar wrote a behavioral description of what you wanted... but you 
could write it using  primitives (d-flipflops and gates) to achieve the 
same result... as you wanted... You may wan to draw the circuit on a 
piece of paper, or you could use the schematic editor that some fpga 
packages provide
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