EmbDev.net

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Subject Author Replies Last post
cannot set sck period. Sungod3k 7
Issue with inout ports bob 1
How to get automatic labels on board Alex 2
debug processor Legacy My 0
schematic diagram of my first pcb board Dushyant Kumar SIngh 3
Unit testing- too much maintenance overhead? R L 3
Communication system: Interleaver Rob Griffin 8
Calculate Sum of (z[n])^2 in VHDL Eric Thompson 4
4.3" LCD Touch Panel LTM Dlitwp S. 5
EFM32 HD44780(KS0066) library Stephan Galitsky 0
Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware verification Jay 1
AVR32 uc3c startup troubleshooting hBechtold 3
Serial signal in DAC angelo 4
Verilog Code Help Navtej Johal 5
AVR ATmega8, cannot transmit multiple characters via UART, data getting lost Alex Kapphahn 1
stop watch using verilog Prasanna M. 1
Comparator 2 Bit Question AOG 4
Thumb mode error Pavel Yermolenko 2
Time Stamping on a Nano second scale Wadood S. 10
max3420e usb Controller Rockyy Sharma 3
STM32F051 I2C slave problem klaus 3
FPGA in CPU socket James Yunker 31
LPC2148 ADC not working properly Siddharth Sharma 0
Atmega 644 mit FTDI 221X über SPI Johannes Walcher 0
Still missing crt0.o Salman Sheikh 3
Problem in real-time data acqusition using Zest Et1 John 1
simulation to implementation, problems with the real type Louis Louis 5
ADT7310 SPI communication Mirko 15
Illegal recursive instantiation Iluvatar 3
Pointer std_logic_vector Kim 6
State Machine with accumulator in VHDL Sony 4
Rectangular waveform generator in the range from 0 to 10MHz. Marek 2
Simple calculator with FPGA Hosein Poorhoseini 5
hardware in loop Mohammad Mothermohammad 0
Laplacian of gaussian edge detection Mark Jomari 1
How to decide the maximum frequency on FPGA? Yang Zheng 4
vhdl test bench Rockyy Sharma 2
Need help to choose FPGA MAINUL ALAM 16
arithmetic operations between logic vectors and constants itay 1
Antenna Selection for 868 MHz transceiver HF 1
Looking for participants in my Altera Music Project Rolf S. 0
design converter on FPGA Mohammad Mothermohammad 2
multiple connection sebgimi 7
looking for a MIPS1 multi cycle, not pipelined Legacy My 16
counter as function itay 1
capacitor in vhdl ? angelo 14
cmos camera raw interface Mark Jomari 3
Will my sonic indicator design fit in a small FPGA? Otto Hunt 1
Problem with set_fs function in 2.4 linux kernel module Yuri Petrovsky 0
Robert and Prewitt Edge Detection Mark Jomari 5
please help edge detection Mark Jomari 7