Wadood S. wrote:
>
> The simple approach I'm trying here is to run a timer with a 1GHz clock
> and whenever the event occurs, save the timer value.So the external
> clock needs to be of time period 1ns.
>
> So can FPGA timers run on the 1GHz processor clock? Or do they run on a
> slower clock?

The FPGA don't have timers out of the box, you have to build them using
the FPGA logic resources. But with most FPGAs you will by far not 
achieve 1 GHz.

>
> Another problem would be the time taken to latch the value of the timer
> to a storage register. Does it take many clock cycles(and which clock)
> or does the latching occur in an analog fashion(on order of
> picoseconds)?
>
> I'm also not an expert on FPGAs and have just worked on
> Micro-controllers previously.
>
> So is this task do-able on FPGAs? And what FPGAs would be suggestable?
> Regards

The task is do-able, but not with just a counter. It is possible to 
exploit the high speed IO Capabilities of a modern FPGA to use a much 
slower clock. The 1 ns should be doable on normal IOs of an actual FPGA 
like Spartan6, Cyclone V, ECP3. With a GT Serdes a higher resoltuion may 
be possible, mabye even 50ps on an Aria 10.

But this tricks require a lot FPGA experience with high speed IO. In 
other words get an expert.

Time to digital converters with multi hit could do that,depending on the 
amount of hits.

http://www.acam.de/products/time-to-digital-converters/tdc-gpx/

Wadood S. wrote:
> I've looked into TDC's. MAX35101, Gp-22, and THS766. I want to use them
> with a micro-controller(or even an fpga) but they don't give out an
> evaluation boards. My budget is under 400 USD.
>
> Googling '1GHz fpga' returns a virtex 7 fpga or a Xilinx-7000.
>
> Wouldn't these things work?

That search term is to unspecific to return useful results. In many 
FPGAs are subsystems which can go beyond 1 GHz, in case of Xilinx Zynq 
7000, this
is probably the ARM core. To build things like counters with the fpga 
you need a FPGA core clock with 1 GHz. The fastet FPGA in the making 
(according to Altera) is the Stratix 10, and will achieve according to 
one source clockrates from 500 - 1000 NHz. Another source put it at 
about 750 MHz. The Stratix 10 is build with Intels 14 nm trigate process 
and amples are planned for next year.

Wadood S. wrote:
> @Lattice User: What technique are you actually suggesting? Is it the
> clock interpolating technique used by TDCs?

I haven't looked at TDCs for a long time, so i don't know.

Many FPGAs have IO blocks, which can do at least DDR clocking, that 
means sampling the signal at both clock edges. This doubles the 
resolution. Some can do even more using phase shiftet clocks, mainly x4 
but x8 is also available in some devices.

With x4 you will get 4 bits with your "slow" clock depending on the 
arrival of the pulse in relation to the clock this will be, 1111, 0111, 
0011, 0001. Enocde these to 2 bits and append it to the captured counter 
value.

It is also doable with an external delay line and using multiple inputs.

The price you pay is an unknown differential error of some 100 ps.

Hello

The ISERDES in a SPARTAN 6 can run at 1050 MHz. 8:1 Radio. LVDS Inputs.

In a Series 7 FPGA it shut be faster.

MfG

Michael

you may try google with the keyword 'flancter'. Then find out if your 
FPGA is fast enough for your problem...