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Subject Author Replies Last post
MATLAB error bora bora 14
packages in vhdl Harry saluja 3
pls help with coding Harry saluja 4
internal current draw on reset pin (ATMEGA48 20AU) Michael 2
Multiple assignments in verilog nelson george 4
VHDL Synthesis Vibhuti R. 3
[vhdl] spi cntroller chike junior 9
floating point / real number soumava roy 5
i2c strange behavior on lpc2148 Gossamer 0
error in place and route step slalas dafvj 10
Change in start up file Rajbabu chouhan 1
PROBLEM WITH CONNECTING SIGNALS ALU TO 4BITADDERSUB Xilinx VHDL 9
Help with State Machine VHDL Eddie Pena 5
EAGLE - forward backward annotations disabled; move command in board disabled Ralf S. 1
error in post place and route simulation sarmad sarmad 6
STR911 ADC analog watchdog Pedro 0
doubt on how to connect the ports in vhdl Elaine San 1
array in veriolg timmy jones 2
coding the vga port keith dunc 6
Zx81 on Avr Atmega1284 David R. 2
MOTOR_SPEED CONTROLLER Ajit kumar 0
Reading program from ATMEGA128 Melvin G. 1
AVR GCC writing a bit from one byte into another Alex P. 10
Can I get help on seperating all the registers in seperate files instead of in a single VHDL file Mohammad Khan 0
Datasheet for unmatched IC Suresh S. 0
8-Bit ALU Model using VHDL John Clark 11
controll only 1 bit from 1 byte micro uc 2
AVR Studio - ATmega8 - display f_cpu on lcd micro uc 4
Microcontroller for Switch Tai Sun 1
Help with VHDL code Eddie Pena 9
SAM7S - Problem With Binary (.Bin) File Create Nazmus Sakib 0
Instantiating signals from the ARCHITECTURE in the test bench FC LOPEZ 9
std_logic_vector to unsigned/signed conversion Gabriel Lozano 5
TMR0 PIC16F917 Dragu Mircea 4
HD44780 LCD with PIC 18F2550 Marius 17
Please help in solving the warning "cast increases required alignment of target type" Karthik C. 2
WinARM arm-elf-objdump Error 126 Laputa 1
loop shifts array entries Henrik 2
Top Entity--D flip flop and Counter Fahim Khan 2
Daisy-chainable communication Schnitzgi 9
undefined reference to `__exidx_start' when starting new system, Nils Soderman 8
I need help with a VHDL average calculator (sum contains 10 products) Henk Haring 2
Check Home Directory C:/Users/Lab. The Environment var. Nils Soderman 2
entity, end of the declaration Marco 2
Network printer interfacing with LPC2478 Swapnil D 2
confused by various UDP checksum algorithms magnetron 9
DDS output - U channel 100 V, I channel 1 A Pavel 3
STM32L1xxx µC displaying memory contents vinay kumar 3
WRF24WB0MA no response to DHCP MAC broadcast Michael 1
concurrent event signals mansoor sharifi 9
Network On Chip mansoor sharifi 2