I'm new to VHDL, and I want to create something that accepts an 8 bit 
input, but has a 16bit data bus (have to add 8 zeros I assume). Be nice 
if there was an overflow bit that went high if the input was valid (not 
too large, less than or equal to 9999). A state machine to control this 
datapath and the start state should remain hi until the input signal is 
brought hi. If the overflow is high, it wont calculate. this and state 
machine have to be integrated together. This is my goal at least, can 
you give me some pointers as to starting this code? Thank you,

John

> I want to create something
What "something" could that be?
What is your actual problem?
Please describe it without your personal interpretation: where does 
the data come from, what must happen with it and where does it go to.