I'd suggest you get a good learning book about Verilog, and read it at
least 3 times. The concepts are not difficult but they are different
from C programming.
You know '<=' is an unblocking assignment, right ? Good:
On the rising edge of the clock all registers will get updated with the
current values that are on the right.
The values in the first example are fixed, then all registers get those
On the second example:
First rising edge
1. s_rot gets s shifted 1 to the left
2. s_2 gets s plus 3
3. s_out gets the current value of s (not yet shifted) plus 1
4. s_out2 gets the current value of s plus whatever value s_2 has
Second rising edge
The same as above... now s_out contains the shifted s plus 1...