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Forum: FPGA, VHDL & Verilog array in veriolg


von timmy j. (Company: CPS) (geekocoder)


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  • array.v (616 Bytes, 333 downloads)

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i am trying to create a 2D array in verilog and trying to initiate the 
values....can anyone plz help me to figure out the flaw in the code 
(attached file)

Any help is highly appreciated

von Oliver H. (ollih)


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As far as I know, verilog doesn't support 2D-arrays. You may define a 
register with a special bitsize as an 1D-array:

reg [1:0] arr [7:0];  // a 2bit wide memory with 8 memory cells

there is no access to a random bit in this array, you may just write 
complete memory cells:

for( i = 0; i<8; i=i+1)   // my verilog simulator doesn't accept "i++"
begin
   for( j=0; j<2; j=j+1 )
   begin
     arr[i] = arr[i] | 1<<j;
   end
end

von Lattice User (Guest)


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>As far as I know, verilog doesn't support 2D-arrays.

Multidimensional arrays are supported since verilog 2001. But many 
toolchains default to verilog 95, even today.

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