array in veriolg

As far as I know, verilog doesn't support 2D-arrays. You may define a 
register with a special bitsize as an 1D-array:

reg [1:0] arr [7:0];  // a 2bit wide memory with 8 memory cells

there is no access to a random bit in this array, you may just write 
complete memory cells:

for( i = 0; i<8; i=i+1)   // my verilog simulator doesn't accept "i++"
begin
   for( j=0; j<2; j=j+1 )
   begin
     arr[i] = arr[i] | 1<<j;
   end
end