Help with State Machine VHDL

Eddie P. (bertswoot) OP 2013-02-24 18:23 #3060150

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I need help with this state Diagram. I think I can write the code for it 
but im a little confused on what the x,x/0 means. Any help would be 
greatly appreciated.

Attached files:

Diagram.png (13 KB)

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Flomobile Guest 2013-02-24 18:58 #3060206

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x,x -> state transition without constraints
0,x -> state transition only when in1=0
...

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Eddie P. (bertswoot) OP 2013-02-24 20:42 #3060348

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY number8 IS
PORT(
CLK        : IN BIT;
IN1, IN2     : IN BIT;
OUT1            : OUT BIT);
END number8;

ARCHITECTURE circuit OF number8 IS
TYPE STATE_TYPE IS (S0, S1, S2, S3, S4, S5, S6, S7);
SIGNAL state   : STATE_TYPE;

BEGIN

PROCESS(CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
CASE state IS
WHEN S0 => state <= S1;
OUT1    <= '0';
WHEN S1 =>
IF IN1 = '1' THEN
state <= S1;
OUT1  <= '0';
ELSIF IN1 = '0' THEN
state <= S2;
OUT1  <= '1';
END IF;
WHEN S2 => state <= S3;
OUT1    <= '0';
WHEN S3 => state <= S4;
OUT1    <= '0';
WHEN S4 =>
IF IN2 = '1' THEN
state <= S4;
OUT1  <= '0';
ELSIF IN2  = '0' THEN
state <= S0;
OUT1  <= '1';
END IF;
WHEN S5 => state <= S0;
WHEN S6 => state <= S0;
WHEN S7 => state <= S0;
END CASE;
END IF;
END PROCESS;
END circuit;






Here is the code I came up with. does it look ok. It compiles fine but I 
havent ran a simulation yet.

Thanks for the input Flomobile!! That was exactly what I needed to know.

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Eddie P. (bertswoot) OP 2013-02-24 21:08 #3060400

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I realized that I still have the Library on there when I didnt use 
STD_logic.

ooops..

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Duke Scarring Guest 2013-02-25 08:57 #3060763

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You also have some superflous states at the moment (S5, S6, S7).
But the simulation looks nice.
And with some formatting the code looks also nice:

entity number8 is
    port(
        CLK      : in  bit;
        IN1, IN2 : in  bit;
        OUT1     : out bit
end number8;
architecture circuit of number8 is
    type   STATE_TYPE is (S0, S1, S2, S3, S4, S5, S6, S7);
    signal state : STATE_TYPE;
    process(CLK)
    begin
        if (CLK'event and CLK = '1') then
            case state is
                when S0 => state <= S1;
                when S1 =>
                    if IN1 = '1' then
                        state <= S1;
                    elsif IN1 = '0' then
                        state <= S2;
                when S2 => state <= S3;
                when S3 => state <= S4;
                when S4 =>
                    if IN2 = '1' then
                        state <= S4;
                    elsif IN2 = '0' then
                        state <= S0;
                when S5 => state <= S0;
                when S6 => state <= S0;
                when S7 => state <= S0;
            end case;
        end if;
    end process;
end circuit;


Duke

Attached files:

state_machine_simulation.png (30 KB)

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Eddie P. (bertswoot) OP 2013-02-25 15:26 #3061295

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Thanks Duke.. I tried copying it from quartus but it wouldnt let me 
paste it on to the thread. But yes my code looked like yours 
(formatting). Thanks for running the simulation and taking the time to 
look at my code I really appreciate it.

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