I need help with this state Diagram. I think I can write the code for it 
but im a little confused on what the x,x/0 means. Any help would be 
greatly appreciated.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY number8 IS
PORT(
CLK        : IN BIT;
IN1, IN2     : IN BIT;
OUT1            : OUT BIT);
END number8;

ARCHITECTURE circuit OF number8 IS
TYPE STATE_TYPE IS (S0, S1, S2, S3, S4, S5, S6, S7);
SIGNAL state   : STATE_TYPE;

BEGIN

PROCESS(CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
CASE state IS
WHEN S0 => state <= S1;
OUT1    <= '0';
WHEN S1 =>
IF IN1 = '1' THEN
state <= S1;
OUT1  <= '0';
ELSIF IN1 = '0' THEN
state <= S2;
OUT1  <= '1';
END IF;
WHEN S2 => state <= S3;
OUT1    <= '0';
WHEN S3 => state <= S4;
OUT1    <= '0';
WHEN S4 =>
IF IN2 = '1' THEN
state <= S4;
OUT1  <= '0';
ELSIF IN2  = '0' THEN
state <= S0;
OUT1  <= '1';
END IF;
WHEN S5 => state <= S0;
WHEN S6 => state <= S0;
WHEN S7 => state <= S0;
END CASE;
END IF;
END PROCESS;
END circuit;






Here is the code I came up with. does it look ok. It compiles fine but I 
havent ran a simulation yet.

Thanks for the input Flomobile!! That was exactly what I needed to know.

I realized that I still have the Library on there when I didnt use 
STD_logic.

ooops..

Thanks Duke.. I tried copying it from quartus but it wouldnt let me 
paste it on to the thread. But yes my code looked like yours 
(formatting). Thanks for running the simulation and taking the time to 
look at my code I really appreciate it.