Help with State Machine VHDL

Eddie P. OP #3060348
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY number8 IS
PORT(
CLK        : IN BIT;
IN1, IN2     : IN BIT;
OUT1            : OUT BIT);
END number8;

ARCHITECTURE circuit OF number8 IS
TYPE STATE_TYPE IS (S0, S1, S2, S3, S4, S5, S6, S7);
SIGNAL state   : STATE_TYPE;

BEGIN

PROCESS(CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
CASE state IS
WHEN S0 => state <= S1;
OUT1    <= '0';
WHEN S1 =>
IF IN1 = '1' THEN
state <= S1;
OUT1  <= '0';
ELSIF IN1 = '0' THEN
state <= S2;
OUT1  <= '1';
END IF;
WHEN S2 => state <= S3;
OUT1    <= '0';
WHEN S3 => state <= S4;
OUT1    <= '0';
WHEN S4 =>
IF IN2 = '1' THEN
state <= S4;
OUT1  <= '0';
ELSIF IN2  = '0' THEN
state <= S0;
OUT1  <= '1';
END IF;
WHEN S5 => state <= S0;
WHEN S6 => state <= S0;
WHEN S7 => state <= S0;
END CASE;
END IF;
END PROCESS;
END circuit;






Here is the code I came up with. does it look ok. It compiles fine but I 
havent ran a simulation yet.

Thanks for the input Flomobile!! That was exactly what I needed to know.
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Duke Scarring Guest #3060763
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You also have some superflous states at the moment (S5, S6, S7).
But the simulation looks nice.
And with some formatting the code looks also nice:
1
entity number8 is

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    port(

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        CLK      : in  bit;

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        IN1, IN2 : in  bit;

5
        OUT1     : out bit

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        );

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end number8;

8


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architecture circuit of number8 is

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    type   STATE_TYPE is (S0, S1, S2, S3, S4, S5, S6, S7);

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    signal state : STATE_TYPE;

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begin

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    process(CLK)

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    begin

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        if (CLK'event and CLK = '1') then

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            case state is

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                when S0 => state <= S1;

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                           OUT1 <= '0';

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                when S1 =>

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                    if IN1 = '1' then

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                        state <= S1;

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                        OUT1  <= '0';

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                    elsif IN1 = '0' then

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                        state <= S2;

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                        OUT1  <= '1';

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                    end if;

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                when S2 => state <= S3;

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                           OUT1 <= '0';

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                when S3 => state <= S4;

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                           OUT1 <= '0';

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                when S4 =>

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                    if IN2 = '1' then

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                        state <= S4;

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                        OUT1  <= '0';

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                    elsif IN2 = '0' then

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                        state <= S0;

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                        OUT1  <= '1';

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                    end if;

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                when S5 => state <= S0;

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                when S6 => state <= S0;

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                when S7 => state <= S0;

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            end case;

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        end if;

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    end process;

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end circuit;


Duke
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