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Forum: FPGA, VHDL & Verilog FPGA Top Module Schematic Problem

von Yigit (Guest)

2012-11-17 22:39

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Hello everybody,

I have been learning VHDL for a month now and am stuck with this project 
in which I am trying to connect a PS2 keyboard to my FPGA board and show 
the letters typed on the 7segment display. I am near to end, however am 
stuck in matching the scancode values with their corresponding 7bit 
binary representations for SSD. I have added a Matcher module of course, 
but I can not add that module to top module properly. Even if it is 
shown under the topmodule, I can not see it in RTL schematic. I am 
adding my Top module and Matcher Module and a SS of my schematic.

The weird thing is that, even though I do not have an output ScanCode in 
my top module, RTL seems to do/behave so.
 I need your help!

Thanks!

Top Module:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Keyboard is
  port (Reset     : in STD_LOGIC;
      Clock     : in STD_LOGIC;
      PS2Clock  : inout STD_LOGIC;
      PS2Data   : inout STD_LOGIC;
      CodeReady : out STD_LOGIC;
      --ScanCode  : out STD_LOGIC_VECTOR(9 downto 0);
      SEGMENTS  : out STD_LOGIC_VECTOR(6 downto 0));
end Keyboard;
architecture Behavioral of Keyboard is
  signal Send      : STD_LOGIC;
  signal Command   : STD_LOGIC_VECTOR(7 downto 0);
  signal PS2Busy   : STD_LOGIC;
  signal PS2Error  : STD_LOGIC;
  signal DataReady : STD_LOGIC;
  signal DataByte  : STD_LOGIC_VECTOR(7 downto 0);
  signal ScanCode  : STD_LOGIC_VECTOR(9 downto 0);
  signal ScanCode2  : STD_LOGIC_VECTOR(7 downto 0);
  PS2_Controller: entity work.PS2Controller
    port map (Reset     => Reset,
          Clock     => Clock,
          PS2Clock  => PS2Clock,
          PS2Data   => PS2Data,
          Send      => Send,
          Command   => Command,
          PS2Busy   => PS2Busy,
          PS2Error  => PS2Error,
          DataReady => DataReady,
          DataByte  => DataByte);
  Keyboard_Mapper: entity work.KeyboardMapper
    port map (Clock     => Clock,
          Reset     => Reset,
          PS2Busy   => PS2Busy,
          PS2Error  => PS2Error,
          DataReady => DataReady,
          DataByte  => DataByte,
          Send      => Send,
          Command   => Command,
          CodeReady => CodeReady,
          ScanCode  => ScanCode);
ScanCode2 <= ScanCode (7 downto 0);
  Matcher: entity work.Matcher
    port map ( SCANCODE => ScanCode2,
          SEGMENTS => SEGMENTS);
end Behavioral;


Matcher Module:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Matcher is
port ( SCANCODE  : in STD_LOGIC_VECTOR(7 downto 0);
     SEGMENTS  : out STD_LOGIC_VECTOR(6 downto 0)
end Matcher;
architecture Behavioral of Matcher is
  process(SCANCODE)
    begin
      case SCANCODE is        
        when "01000101" => SEGMENTS <= "0111111"; -- 0
        when "00010110" => SEGMENTS <= "0000110"; -- 1
        when "00011110" => SEGMENTS <= "1011011"; -- 2
        when "00100110" => SEGMENTS <= "1001111"; -- 3
        when "00100101" => SEGMENTS <= "1100110"; -- 4
        when "00101110" => SEGMENTS <= "1101101"; -- 5
        when "00110110" => SEGMENTS <= "1111101"; -- 6
        when "00111101" => SEGMENTS <= "0000111"; -- 7
        when "00111110" => SEGMENTS <= "1111111"; -- 8
        when "01000110" => SEGMENTS <= "1101111"; -- 9
        when "00011100" => SEGMENTS <= "1110111"; -- A
        when "00110010" => SEGMENTS <= "1111100"; -- b
        when "00100001" => SEGMENTS <= "0111001"; -- C
        when "00100011" => SEGMENTS <= "1011110"; -- d
        when "00100100" => SEGMENTS <= "1111001"; -- E
        when "00101011" => SEGMENTS <= "1110001"; -- F
        when "00110100" => SEGMENTS <= "1100111"; -- g
        when "00110011" => SEGMENTS <= "1110110"; -- H
        when "01000011" => SEGMENTS <= "0110000"; -- I
        when "00111011" => SEGMENTS <= "0011110"; -- J
        when "01000010" => SEGMENTS <= "1110101"; -- K
        when "01001011" => SEGMENTS <= "0111000"; -- L
        when "00111010" => SEGMENTS <= "0010101"; -- M
        when "00110001" => SEGMENTS <= "1010100"; -- n
        when "01000100" => SEGMENTS <= "1011100"; -- o
        when "01001101" => SEGMENTS <= "1110011"; -- P
        when "00101101" => SEGMENTS <= "1010000"; -- r
        when "00101100" => SEGMENTS <= "1111000"; -- t
        when "00111100" => SEGMENTS <= "0111110"; -- u
        when "00101010" => SEGMENTS <= "0011100"; -- v
        when "00110101" => SEGMENTS <= "1101110"; -- y
        when others => SEGMENTS <= "1001001"; -- Error!
      end case;
    -- SelectDisplay <= AN; -- the segment(s) we choose via the pins on the board will be enabled.
  end process;
end Behavioral;

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Re: FPGA Top Module Schematic Problem

von Yigit (Guest)

2012-11-17 23:28

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A little update here. Now everything seems properly placed, I recreated 
the project, I guess there was a problem with file locations. Now, I 
seem to get error case everytime. Any help?

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Re: FPGA Top Module Schematic Problem

von DuArte (Guest)

2012-11-20 09:09

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>A little update here. Now everything seems properly placed

Please show the schematic to us

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Re: FPGA Top Module Schematic Problem

von Yigit (Guest)

2012-11-20 19:54

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Hello again,

I managed to properly obtain the scancodes, and also managed to properly 
display them. I changed my design completely though, so there is no need 
to show any schematics of the previous codes. Now, Im thinking of 
displaying up to 4 letters side to side, but I can not think of any way. 
Only idea I have is to mux the displays, but I dont know how to assign 
different outputs to different displays. Any help will be appreciated, 
no need to be code blocks, I prefer study materials in fact. Thanks!

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Re: FPGA Top Module Schematic Problem

von Lothar M. (lkmiller) (Moderator)

2012-11-20 20:52

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So 1. build a (very small) 4 word first-in-first-out Memory with 
parallel access where you read in one key after the other
then 2. activate the leftmost digit (a hint: commong cathode or anode) 
and give the leftmost cell of the fifo to the common 7 lines
then 3. activate the second digit and display the next character
then 4. same with the next word
then 5. same with the rightmost digit and the last word in memory
after that 6. repeat steps 2 to 5 with appx. 100Hz.

Thats all.

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Re: FPGA Top Module Schematic Problem

von marie (Guest)

2013-03-12 01:39

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So, can you send me the final code (just for one single 7 seg)??
I'm trying to do the same project and it's never working!!
What did you find out?

Thanks a lot!

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Re: FPGA Top Module Schematic Problem

von Lothar M. (lkmiller) (Moderator)

2013-03-12 06:13

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marie wrote:
> I'm trying to do the same project and it's never working!!
So: show your code and tell whats wrong with it.

> So, can you send me the final code (just for one single 7 seg)??
A code looking good enough can be found in the "matcher" module in the 
initial post of this thread.

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