Hello everybody,
I have been learning VHDL for a month now and am stuck with this project
in which I am trying to connect a PS2 keyboard to my FPGA board and show
the letters typed on the 7segment display. I am near to end, however am
stuck in matching the scancode values with their corresponding 7bit
binary representations for SSD. I have added a Matcher module of course,
but I can not add that module to top module properly. Even if it is
shown under the topmodule, I can not see it in RTL schematic. I am
adding my Top module and Matcher Module and a SS of my schematic.
The weird thing is that, even though I do not have an output ScanCode in
my top module, RTL seems to do/behave so.
I need your help!
Thanks!
Top Module:
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libraryIEEE;
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useIEEE.STD_LOGIC_1164.ALL;
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useIEEE.STD_LOGIC_ARITH.ALL;
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useIEEE.STD_LOGIC_UNSIGNED.ALL;
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entityKeyboardis
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port(Reset:inSTD_LOGIC;
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Clock:inSTD_LOGIC;
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PS2Clock:inoutSTD_LOGIC;
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PS2Data:inoutSTD_LOGIC;
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CodeReady:outSTD_LOGIC;
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--ScanCode : out STD_LOGIC_VECTOR(9 downto 0);
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SEGMENTS:outSTD_LOGIC_VECTOR(6downto0));
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endKeyboard;
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architectureBehavioralofKeyboardis
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signalSend:STD_LOGIC;
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signalCommand:STD_LOGIC_VECTOR(7downto0);
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signalPS2Busy:STD_LOGIC;
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signalPS2Error:STD_LOGIC;
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signalDataReady:STD_LOGIC;
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signalDataByte:STD_LOGIC_VECTOR(7downto0);
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signalScanCode:STD_LOGIC_VECTOR(9downto0);
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signalScanCode2:STD_LOGIC_VECTOR(7downto0);
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begin
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PS2_Controller:entitywork.PS2Controller
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portmap(Reset=>Reset,
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Clock=>Clock,
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PS2Clock=>PS2Clock,
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PS2Data=>PS2Data,
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Send=>Send,
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Command=>Command,
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PS2Busy=>PS2Busy,
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PS2Error=>PS2Error,
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DataReady=>DataReady,
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DataByte=>DataByte);
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Keyboard_Mapper:entitywork.KeyboardMapper
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portmap(Clock=>Clock,
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Reset=>Reset,
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PS2Busy=>PS2Busy,
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PS2Error=>PS2Error,
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DataReady=>DataReady,
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DataByte=>DataByte,
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Send=>Send,
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Command=>Command,
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CodeReady=>CodeReady,
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ScanCode=>ScanCode);
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ScanCode2<=ScanCode(7downto0);
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Matcher:entitywork.Matcher
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portmap(SCANCODE=>ScanCode2,
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SEGMENTS=>SEGMENTS);
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endBehavioral;
Matcher Module:
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libraryIEEE;
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useIEEE.STD_LOGIC_1164.ALL;
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entityMatcheris
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port(SCANCODE:inSTD_LOGIC_VECTOR(7downto0);
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SEGMENTS:outSTD_LOGIC_VECTOR(6downto0)
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);
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endMatcher;
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architectureBehavioralofMatcheris
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begin
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process(SCANCODE)
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begin
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caseSCANCODEis
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when"01000101"=>SEGMENTS<="0111111";-- 0
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when"00010110"=>SEGMENTS<="0000110";-- 1
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when"00011110"=>SEGMENTS<="1011011";-- 2
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when"00100110"=>SEGMENTS<="1001111";-- 3
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when"00100101"=>SEGMENTS<="1100110";-- 4
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when"00101110"=>SEGMENTS<="1101101";-- 5
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when"00110110"=>SEGMENTS<="1111101";-- 6
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when"00111101"=>SEGMENTS<="0000111";-- 7
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when"00111110"=>SEGMENTS<="1111111";-- 8
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when"01000110"=>SEGMENTS<="1101111";-- 9
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when"00011100"=>SEGMENTS<="1110111";-- A
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when"00110010"=>SEGMENTS<="1111100";-- b
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when"00100001"=>SEGMENTS<="0111001";-- C
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when"00100011"=>SEGMENTS<="1011110";-- d
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when"00100100"=>SEGMENTS<="1111001";-- E
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when"00101011"=>SEGMENTS<="1110001";-- F
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when"00110100"=>SEGMENTS<="1100111";-- g
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when"00110011"=>SEGMENTS<="1110110";-- H
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when"01000011"=>SEGMENTS<="0110000";-- I
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when"00111011"=>SEGMENTS<="0011110";-- J
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when"01000010"=>SEGMENTS<="1110101";-- K
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when"01001011"=>SEGMENTS<="0111000";-- L
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when"00111010"=>SEGMENTS<="0010101";-- M
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when"00110001"=>SEGMENTS<="1010100";-- n
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when"01000100"=>SEGMENTS<="1011100";-- o
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when"01001101"=>SEGMENTS<="1110011";-- P
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when"00101101"=>SEGMENTS<="1010000";-- r
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when"00101100"=>SEGMENTS<="1111000";-- t
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when"00111100"=>SEGMENTS<="0111110";-- u
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when"00101010"=>SEGMENTS<="0011100";-- v
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when"00110101"=>SEGMENTS<="1101110";-- y
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whenothers=>SEGMENTS<="1001001";-- Error!
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endcase;
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-- SelectDisplay <= AN; -- the segment(s) we choose via the pins on the board will be enabled.
A little update here. Now everything seems properly placed, I recreated
the project, I guess there was a problem with file locations. Now, I
seem to get error case everytime. Any help?
Hello again,
I managed to properly obtain the scancodes, and also managed to properly
display them. I changed my design completely though, so there is no need
to show any schematics of the previous codes. Now, Im thinking of
displaying up to 4 letters side to side, but I can not think of any way.
Only idea I have is to mux the displays, but I dont know how to assign
different outputs to different displays. Any help will be appreciated,
no need to be code blocks, I prefer study materials in fact. Thanks!
So 1. build a (very small) 4 word first-in-first-out Memory with
parallel access where you read in one key after the other
then 2. activate the leftmost digit (a hint: commong cathode or anode)
and give the leftmost cell of the fifo to the common 7 lines
then 3. activate the second digit and display the next character
then 4. same with the next word
then 5. same with the rightmost digit and the last word in memory
after that 6. repeat steps 2 to 5 with appx. 100Hz.
Thats all.
So, can you send me the final code (just for one single 7 seg)??
I'm trying to do the same project and it's never working!!
What did you find out?
Thanks a lot!
marie wrote:> I'm trying to do the same project and it's never working!!
So: show your code and tell whats wrong with it.
> So, can you send me the final code (just for one single 7 seg)??
A code looking good enough can be found in the "matcher" module in the
initial post of this thread.