Top Entity--D flip flop and Counter

Fahim K. (fahimk) OP 2013-01-14 15:39 #2997901

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Hi,

I am writing entity which include both d flip flop and counter.
The output of d flip flop is qout and nqout. The qout is given as input 
to counter. Now while writing top entity I am considering qout and nqout 
as temporary signal. And its working fine. But I want to modify it such 
that these signal becomes my port and I can use it to excite some other 
circuit.
My code is as below.

library ieee;
use ieee.std_logic_1164.all;
entity dff is
port ( din:     in std_logic;
       dclk:     in std_logic;
       qout:    out std_logic;
       nqout:   out std_logic
end dff;
architecture behavioral of dff is
        process(din,dclk)
        begin
          --- clock rising edge
        if(dclk='1' and dclk'event) then
                qout <= din;
                nqout <= not din;
        end if;
        end process;
end behavioral;
--UpdownCounter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter is
generic(n: natural :=8);
port ( asynch_reset: in std_logic;
       qout: in std_logic;
       dclk: in std_logic;
       cnout: out std_logic_vector(n-1 downto 0)
end counter;
architecture behavioral of counter is
signal Q: unsigned(n-1 downto 0);
    process(asynch_reset, dclk,qout)
        begin
          if(asynch_reset = '1') then
          elsif (dclk'event and dclk = '1') then
                if (qout='1') then
                end if;
          end if;
    end process;
    cnout<=     std_logic_vector(Q);
end behavioral;
----Top Entity
library ieee ;
use ieee.std_logic_1164.all;
entity top is
generic(n: natural :=8);
port(  din: in std_logic;
       asynch_reset: in std_logic;  
       dclk: in std_logic;
       cnout: out std_logic_vector(n-1 downto 0)
end top;
architecture structure of top is
component dff is
port( din: in std_logic;
      dclk: in std_logic;
      qout: out std_logic;
      nqout: out std_logic
end component;
component counter is
port( asynch_reset: in std_logic;
      qout: in std_logic;
      dclk:in std_logic;
      cnout:out std_logic_vector(n-1 downto 0)
end component;
signal temp1,temp2:std_logic;
flip_flop:dff
    PORT MAP(din,dclk,temp1,temp2);
updown_counter:counter
         PORT MAP(asynch_reset,temp1,dclk,cnout);
end structure;

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