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Forum: FPGA, VHDL & Verilog Top Entity--D flip flop and Counter


von Fahim K. (fahimk)


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Hi,

I am writing entity which include both d flip flop and counter.
The output of d flip flop is qout and nqout. The qout is given as input 
to counter. Now while writing top entity I am considering qout and nqout 
as temporary signal. And its working fine. But I want to modify it such 
that these signal becomes my port and I can use it to excite some other 
circuit.
My code is as below.
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---DFF
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library ieee;
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use ieee.std_logic_1164.all;
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entity dff is
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port ( din:     in std_logic;
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       dclk:     in std_logic;
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       qout:    out std_logic;
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       nqout:   out std_logic
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     );
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end dff;
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architecture behavioral of dff is
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begin
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        process(din,dclk)
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        begin
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          --- clock rising edge
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        if(dclk='1' and dclk'event) then
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                qout <= din;
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                nqout <= not din;
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        end if;
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        end process;
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end behavioral;
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--UpdownCounter
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity counter is
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generic(n: natural :=8);
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port ( asynch_reset: in std_logic;
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       qout: in std_logic;
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       dclk: in std_logic;
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       cnout: out std_logic_vector(n-1 downto 0)
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     );
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end counter;
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architecture behavioral of counter is
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signal Q: unsigned(n-1 downto 0);
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begin
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    process(asynch_reset, dclk,qout)
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        begin
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          if(asynch_reset = '1') then
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                Q<="00000000";
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          elsif (dclk'event and dclk = '1') then
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                if (qout='1') then
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                        Q<= Q + 1;
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                else
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                        Q<= Q - 1;
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                end if;
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          end if;
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    end process;
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    cnout<=     std_logic_vector(Q);
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end behavioral;
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----Top Entity
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library ieee ;
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use ieee.std_logic_1164.all;
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entity top is
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generic(n: natural :=8);
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port(  din: in std_logic;
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       asynch_reset: in std_logic;  
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       dclk: in std_logic;
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       cnout: out std_logic_vector(n-1 downto 0)
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     );
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end top;
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architecture structure of top is
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component dff is
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port( din: in std_logic;
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      dclk: in std_logic;
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      qout: out std_logic;
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      nqout: out std_logic
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    );
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end component;
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component counter is
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port( asynch_reset: in std_logic;
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      qout: in std_logic;
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      dclk:in std_logic;
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      cnout:out std_logic_vector(n-1 downto 0)
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    );
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end component;
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signal temp1,temp2:std_logic;
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begin
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flip_flop:dff
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    PORT MAP(din,dclk,temp1,temp2);
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updown_counter:counter
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         PORT MAP(asynch_reset,temp1,dclk,cnout);
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end structure;

von Lothar M. (lkmiller) (Moderator)


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Fahim Khan wrote:
> But I want to modify it such that these signal becomes my port
Of which entity?
> and I can use it to excite some other circuit.
Connectet to where?

von Fahim K. (fahimk)


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Actually I want to use that signal as port so that I can give it to some 
other part of circuit let say to some analog part. I want it to include 
in my top entity as port not as signal.

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