Hi,
I am writing entity which include both d flip flop and counter.
The output of d flip flop is qout and nqout. The qout is given as input
to counter. Now while writing top entity I am considering qout and nqout
as temporary signal. And its working fine. But I want to modify it such
that these signal becomes my port and I can use it to excite some other
circuit.
My code is as below.
1 | ---DFF
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2 |
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3 | library ieee;
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4 | use ieee.std_logic_1164.all;
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5 |
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6 | entity dff is
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7 | port ( din: in std_logic;
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8 | dclk: in std_logic;
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9 | qout: out std_logic;
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10 | nqout: out std_logic
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11 | );
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12 |
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13 | end dff;
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14 |
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15 | architecture behavioral of dff is
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16 |
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17 | begin
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18 | process(din,dclk)
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19 | begin
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20 | --- clock rising edge
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21 | if(dclk='1' and dclk'event) then
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22 | qout <= din;
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23 | nqout <= not din;
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24 | end if;
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25 | end process;
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26 | end behavioral;
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27 |
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28 |
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29 | --UpdownCounter
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30 |
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31 | library ieee;
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32 | use ieee.std_logic_1164.all;
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33 | use ieee.numeric_std.all;
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34 |
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35 | entity counter is
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36 | generic(n: natural :=8);
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37 | port ( asynch_reset: in std_logic;
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38 | qout: in std_logic;
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39 | dclk: in std_logic;
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40 | cnout: out std_logic_vector(n-1 downto 0)
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41 | );
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42 | end counter;
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43 |
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44 | architecture behavioral of counter is
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45 |
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46 | signal Q: unsigned(n-1 downto 0);
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47 | begin
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48 |
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49 | process(asynch_reset, dclk,qout)
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50 | begin
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51 |
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52 | if(asynch_reset = '1') then
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53 | Q<="00000000";
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54 | elsif (dclk'event and dclk = '1') then
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55 | if (qout='1') then
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56 | Q<= Q + 1;
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57 | else
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58 | Q<= Q - 1;
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59 | end if;
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60 | end if;
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61 | end process;
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62 |
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63 | cnout<= std_logic_vector(Q);
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64 | end behavioral;
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65 |
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66 | ----Top Entity
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67 | library ieee ;
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68 | use ieee.std_logic_1164.all;
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69 |
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70 | entity top is
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71 | generic(n: natural :=8);
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72 | port( din: in std_logic;
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73 | asynch_reset: in std_logic;
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74 | dclk: in std_logic;
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75 | cnout: out std_logic_vector(n-1 downto 0)
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76 | );
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77 |
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78 | end top;
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79 |
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80 | architecture structure of top is
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81 |
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82 | component dff is
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83 | port( din: in std_logic;
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84 | dclk: in std_logic;
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85 | qout: out std_logic;
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86 | nqout: out std_logic
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87 | );
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88 | end component;
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89 |
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90 | component counter is
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91 | port( asynch_reset: in std_logic;
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92 | qout: in std_logic;
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93 | dclk:in std_logic;
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94 | cnout:out std_logic_vector(n-1 downto 0)
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95 | );
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96 | end component;
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97 |
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98 | signal temp1,temp2:std_logic;
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99 |
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100 | begin
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101 |
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102 | flip_flop:dff
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103 | PORT MAP(din,dclk,temp1,temp2);
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104 |
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105 | updown_counter:counter
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106 | PORT MAP(asynch_reset,temp1,dclk,cnout);
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107 | end structure;
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