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Forum: FPGA, VHDL & Verilog coding the vga port


von keith d. (Company: univ) (kth)


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im trying to display a red box on a 640 by 480 screen however nothing is 
displayed on my vga screen im using nexys 3 and these were the port used
clk v10 ns-n6 vs -p7 red1 -u7 green2 - p8 blue2 -r7 here under is my 
code which i made thanks i appriate any help
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 library IEEE; 
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use IEEE.std_logic_1164.all; 
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use IEEE.std_logic_arith.all; 
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use IEEE.std_logic_misc.all; 
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use IEEE.std_logic_unsigned.all; 
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entity vga is
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  port(clk :in std_logic;
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      hs : out std_logic;
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      vs : out std_logic;
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      red1 : out std_logic;
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      green2 : out std_logic;
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blue2: out std_logic
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      );
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            end vga;
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Architecture vga_arch of vga is
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  begin 
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   process(CLK) 
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      variable v :std_logic:= '0';
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      variable h : std_logic := '1' ;
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      variable red :std_logic:= '0';
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      variable green :std_logic:= '0';
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      variable blue :std_logic:= '0';
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       variable x : std_logic_vector(9 downto 0) := "0000000000"  ;
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       variable y  : std_logic_vector(9 downto 0) := "0000000000"  ;
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     begin
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if (CLK'EVENT and CLK = '1') then
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      if(h = '1') then 
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        x := x+ "0000000001" ;
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        if(x = "1010000001") then
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          h:= '0';
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          v := '1';
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          x := "0000000000";
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        end if;
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    elsif(v = '1') then
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    y := y + "0000000001";
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     V:='0';
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     h:='1';
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      end if;
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      if(y = "0111100001") then 
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        y := "0000000000";
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      end if;
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      hs <= h;
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      vs<= v;
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      red1 <='1';
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      blue2 <='0';
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      green2 <='0';
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       end if;
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    end process;
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    end vga_arch;

von Gustl B. (-gb-)


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von keith d. (Company: univ) (kth)


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i arange the code to 60 hz clock cycle but still nothing

von Gustl B. (-gb-)


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http://tinyvga.com/vga-timing/640x480@60Hz

You have to implement everything, front-porch, back-porch, sync-pulse 
...
This is my 1024x768 pixel vga. you can us ist freely and fit it to your 
needs (adapt the timings).
In my case gave the horizontal and vertical counters OUT and generated 
in another module the bin IN signal. This draws an white pixel when bin 
is 1.
The needed 75mhz clock can be generated using an dcm.
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--1024x768 VGA
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--if bin='1' then pixel is white
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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entity vga is
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  port(clk75_in, bin  : in std_logic;
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     horizontal_counter : out std_logic_vector (10 downto 0);
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     vertical_counter   : out std_logic_vector (9 downto 0);
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       red_out   : out std_logic_vector(2 downto 0);
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       green_out : out std_logic_vector(2 downto 0);
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       blue_out  : out std_logic_vector(1 downto 0);
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       hs_out    : out std_logic;
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       vs_out    : out std_logic);
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end vga;
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architecture Behavioral of vga is
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signal hc: integer range 0 to 1328;
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signal vc: integer range 0 to 806;
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begin
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horizontal_counter <= std_logic_vector(to_unsigned(hc,11));
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vertical_counter <= std_logic_vector(to_unsigned(vc,10));
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--Picture starts with sync-pulse
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process
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begin
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  wait until rising_edge(clk75_in);
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    if (hc >= 280 ) -- 280 = Sync-pulse + Back-porch
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    and (hc < 1304 ) -- 1304 = Sync-pulse + Back-porch + Visible-area
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    and (vc >= 35 ) -- 35 = Sync-pulse + Back-porch
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    and (vc < 803 ) -- 803 = Sync-pulse + Back-porch + Visible-area
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    then
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    if bin = '1' then
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      red_out <= "111";
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      green_out <= "111";
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      blue_out <= "11";
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    elsif bin = '0' then
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      red_out <= "000";
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      green_out <= "000";
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      blue_out <= "00";
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    end if;
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    else
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      red_out <= "000";
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      green_out <= "000";
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      blue_out <= "00";
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    end if;
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    if (hc > 0 )
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      and (hc < 136 ) -- 136 = Sync-pulse
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    then
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      hs_out <= '0';
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    else
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      hs_out <= '1';
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    end if;
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    if (vc > 0 )
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      and (vc < 6 ) -- 6 = Sync-pulse
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    then
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      vs_out <= '0';
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    else
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      vs_out <= '1';
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    end if;
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    hc <= hc + 1;
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    if (hc = 1328) then --1328 = Whole-line
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      vc <= vc + 1;
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      hc <= 0;
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    end if;
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    if (vc = 806) then  --806  = Whole-frame    
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      vc <= 0;
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    end if;
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end process;
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end Behavioral;

von René D. (Company: www.dossmatik.de) (dose)


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In this document is the resolution 640x480 simulated and after fitted on 
spartan3an700 board.

http://www.dossmatik.de/ghdl/ghdl_unisim.pdf              german
http://www.dossmatik.de/ghdl/ghdl_unisim_eng.pdf          english

von Kasturi K. (kasturikishore)


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anyone pls help me. I want code in vhdl for hexa decimal inputs. what is 
the port command if i like to give hexadecimal input?

von Lothar M. (lkmiller) (Moderator)


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Don't hijack an old thread with a completely different question!
Start a new thread instead!

And then post all of your information belonging to the problem:
Why do you want to read data?
Where does it come from?
Where does is go to?
What should happen with it?

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