doubt on how to connect the ports in vhdl

Lothar M. Moderator (Company: Titel) #3045746
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Take ANY book about VHDL synthesis and look on the very first pages...

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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entity InToOut is

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    Port ( output : out STD_LOGIC;

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           input  : in  STD_LOGIC);

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end InToOut;

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architecture Behavioral of InToOut is

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begin

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  output <= input;

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end Behavioral;
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