I'm doing a vhdl code and need to connect the input directly at the exit, as I do this? Always connect the main exit at the exit doors ands, ors, etc..
Take ANY book about VHDL synthesis and look on the very first pages...
entity InToOut is
Port ( output : out STD_LOGIC;
input : in STD_LOGIC);
architecture Behavioral of InToOut is
output <= input;