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Forum: FPGA, VHDL & Verilog FPGA tool on Android


Author: Guosheng Wu (Guest)
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Imagine that when you are waiting for a bus, on a business travel or 
laying on the bed, suddenly a genius idea for a piece of hardware 
showing to your mind, how can you implement it with just mobile phones 
or tablets? Robei runs on any Android platform, you can implement your 
design and test it immediately in such situation.

Currently, Robei released 2.1 version on Windows and Android platform. 
You can share the same model on android platform and windows platform.

Website: http://robei.com

Author: Spoiler (Guest)
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Apart from having a strong smell of an ad:
The idea is interesting, but it won't beat a simple piece of paper and a 
pencil.

Author: Most interesting hardware engineer genius (Guest)
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I don't always wait for the bus, but when I do, I prefer writing VHDL 
code

Author: Ale (Guest)
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The idea is not bad, sadly i have an iPad :).

The problem is writing code that needs loads of ( and  [ and { and . and 
, and so on with the built-in on-screen keyboard, at least on the iPad 
it is an exercise on futility :(.

Author: Dave (Guest)
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>it is an exercise on futility

On the other hand, that really shortens the (bus) waiting time ;-)

Author: facts, not ads (Guest)
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>Author: Dave (Guest)


>>it is an exercise on futility

>On the other hand, that really shortens the (bus) waiting time ;-)

Nope, nothing shortens, you just substitute bus waiting time for 
simulation waiting time. And add the effort of having your source code 
and simu results synchronized with your files on the workstation.
It's a toy - not a tool.

Best regards,

Author: markus (Guest)
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I like it, to try out some hardwaresituation not more not less. It is a 
little developement fun. But do this tool run fast enough on a Android 
smartphone to have fun?

Author: Guosheng Wu (Guest)
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You don't want to design whole project on android tablet. Part of your 
project can be done easily with Robei, and the simulation speed is fast 
enough. With the GUI design and code generation, it already reduced the 
code writing. You can just focus on your algorithm code. Play with it, 
you will find answers. It  is still improving.

Author: Daniel (Guest)
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Nice - but it does not support VHDL.
So with this handycap I could not use this tool.

Author: Robei LLC (Guest)
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Compare with other EDA tool, Robei is very unique. The major reasons are 
here:

1. In the past, there were only schematic based design tools which are 
pure diagram design without flexibility of coding. They were great for 
interface and visualization but lack of the flexibility of algorithm 
design. Current design tools are pure code based which provide enough 
flexibility but reduced the intuitive. Robei combined both the 
advantages of diagram design and code design. It enables diagram based 
design on interface, code input method for algorithm.

2. Robei has Android version, which makes it the first EDA tool on 
mobile platform. We did a survey on Robei.com, 80% people would like to 
try on Android. The Android version has all same functions as Windows 
version. You can transfer your design from windows to Android without 
any modification.

3. Transparent IP: IP is good for fast prototyping and short time to 
market. However, we cannot just teach student on how to use IP, 
otherwise, they will be IP Application Engineering instead of FPGA 
Engineering. All Robei’s models are transparent, you can open and edit, 
save them to your own IPs. The tool will lead student to think, focus on 
algorithm and innovation.

4. Many professors complain that FPGA cannot attract their interest. 
Even at the beginning, they have great passion to learn FPGA, but few 
can keep this passion until the semester finish. But every student can 
play with ARM, even without professor’s guidance. That is because FPGA 
design is not intuitive. FPGA design tool is more complex than ARM 
development environment and not very user friendly. In order to attract 
them, Robei implemented with modern user interface, intuitive design, 
simulation and working on mobile platform features.

5. Robei University Program welcomes all professors to join. In this 
program, we provide some free group licenses, design examples and 
training materials for education and research.

Hope this would be useful for you to know this tool.

Author: Robei LLC (Guest)
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Simulation example. See, it is not a toy, it works!

Author: bünjamin (Guest)
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come on! such a simple example can be simulated on paper

Author: Schlumpf (Guest)
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"See, it is not a toy, it works!"

Ahhh everything that "works" is not a toy?

Maby ist´s nice for playing with some verilog-snippets for educational 
purpose but for real fpga-development (even for parts of it) it seems a 
litte bit undersized.

If an pfga-designer stucks and has the great idea in the bus, he will 
paint some block-scematic on a piece of paper.

What I want to say is:
It looks really nice and for sure it was a lot of work to program it. 
And for sure it´s nice for beginners to play a little bit and learn. But 
for developers it seems more or less worthless.

Author: Robei LLC (Guest)
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Schlumpf,

     Robei has a back end verilog compiler, it supports verilog compile 
and simulation. Engineers should judge based on experiment result, not 
based on guess. We would like to see your suggestions and feedback, not 
just guess from assumption. By the way, we have float point unit design 
and we are working on 32 bit CPU design. Hope these are small enough on 
your paper.

Thanks!

Author: Schlumpf (Guest)
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writing code on a smartphone sucks.
Using predefined blocks for simlpe things is much more work than to code 
it in 5 lines... --> also sucks.
Making clock division like in your screenshot from 2013-03-08 23:49 
shows that this code will result in a not really good code for 
synthesis.

I still cannot see any sense for fpga-developers.

Author: Robei LLC (Guest)
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Again, this tool is targeting to entry level to middle level engineer. 
If you feel good to write code, that is a preference. Robei generate 
code from your design which can reduce coding on mobile platform as you 
already told "coding on smartphone sucks".

   Robei never asked you to use predefined blocks for your design, 
instead, you can customer your design by creating a new one with few 
line of code inside.

    Last, you guess again. From the block, you can not see code. How can 
you sure it can not make a good synthesis? This example's source code is 
taking from a text book.

   So, try it out, let me know what you think. I really want to know how 
do you feel after successfully running some examples.

Author: Schlumpf (Guest)
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>>Again, this tool is targeting to entry level to middle level engineer.

This ist what I said! Good to play a little bit around to get familiar 
wih hdl or maybe make a very tiny design. So where is your problem?

>>Last, you guess again. From the block, you can not see code. How can
>>you sure it can not make a good synthesis? This example's source code is
>>taking from a text book.

Because the clock of the divider is used as clock for the following 
block.
This leads to gated clocks, which is cruel :-)

>>So, try it out, let me know what you think. I really want to know how
>>do you feel after successfully running some examples.

Implement VHDL and I probably play a little bit around..

Where is your problem?
You make ads for your app in this forum.
What replies do you expect? MUST everybody say "Whow, this is a 
revoultion. It simplifies my daily work! Robei we love you so much! You 
must be the messias!"?
If you post an advertisment in a FORUM you must accept that people 
answer and give some statements. And this statements CAN be negative 
even without testing the tool.

>>you can customer your design by creating a new one with few
>>line of code inside.

no fpga-designer handles hundrets of small blocks with "few lines of 
code inside"

Author: urop (Guest)
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> no fpga-designer handles hundrets of small blocks
> with "few lines of code inside"

I think you could do that in MATLAB if you wanted to, I've seen large 
designs done by universities using MATLAB and this sysgen stuff, though 
most these blocks did not contain code they wrote themself but were 
predefined stuff.
Matlab is too expensive of course so I never used that myself for real 
work ;-)

Robei may be cheap, but does not look like it is capable of handling 
large designs and I am not sure how well it integrates with the FPGA 
vendor tools.

Oh and yeah lack of VHDL is a major drawback - this is a European Forum 
so you will not find too many Verilog Users here.

Author: Robei LLC (Guest)
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This software can generate Verilog code for all other EDA tools. I 
already collect all the responses.

   VHDL is the next step. I posted it here 2 years ago, expect real 
user's feedback like bugs.

    Some engineers is hard to promote to try it. That is OK. All the 
feedback  are important to us, even the user we can never reach.

   Matlab is good tool, if you can afford the software, but it is 
targeting to people who use Matlab to program. Robei is targeting to 
engineers who use Verilog to program. You will feel all Verilog code is 
yours, and it is easy to find bugs. Also the price is much cheaper.

   Robei works on any size design. It has visual method on each layer. 
So each layer can be a sub-module, then reused for another module. There 
is no limited for your design.

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