error in place and route step

I'm wondering about the high number of latches and clocks in that 
design...

> device is spartan 3e
Which one?

thank you for your answer
my device is spartan3e xc3s500e-4fg320
how can reduce the number of latch and number of clk?

> how can reduce the number of latch
Just don't describe latches in your design.
And therefore you must first be able to recognize latches in your 
design: latches are level sensitive "flipflops".
BTW: is it a VHDL or a Verilog design?

> and number of clk?
Answer this question first: how many clocks do you need at all?
If you don't know an answer, then the correct answer may be: ONE!

my design written in VHDL code
i need one clock for all design how can archive this?

> i need one clock for all design how can archive this?
Usually this is the clock from a xtal-oscillator in the range of 
30..100MHz. And these descritpion result in a clocked flipflop in a VHDL 
design:

1

 if clk50MHz'event and  clk50MHz='1' then

2

  :

3

 if rising_edge(clk50MHz) then

4

  :

5

 if falling_edge(clk50MHz) then

6

  :

7

 wait until clk50MHz'event and  clk50MHz='1';

8

  :

9

 wait until rising_edge(clk50MHz);

10

  :

11

 wait until falling_edge(clk50MHz);

So whereever a similar construct appears, there must be used the same 
signal. Then you have only one clock source over the whole FPGA.

i use
if(clk'event and clk='1') then
-------------
-------------
end if;


for 18 times
but the BUFGMUX is 18 from 24 why??

yes is same signal for all design