help me please in my design this error appear in place and route step tha target device is spartan 3e and the ise is ise14.1 error: Place:120 - There were not enough sites to place all selected components. Some of these failures can be circumvented by using an alternate algorithm (though it may take longer run time). If you would like to enable this algorithm please set the environment variable XIL_PAR_ENABLE_LEGALIZER to 1 and try again and the utilization summary is attached why this error occurs and how can overcome this error please?
> and the utilization summary is attached > why this error occurs and how can overcome this error please? In your report no ressource is used more than 100%. Try to "Cleanup Project Files" and generate the report again. Duke
I'm wondering about the high number of latches and clocks in that design... > device is spartan 3e Which one?
thank you for your answer my device is spartan3e xc3s500e-4fg320 how can reduce the number of latch and number of clk?
> how can reduce the number of latch Just don't describe latches in your design. And therefore you must first be able to recognize latches in your design: latches are level sensitive "flipflops". BTW: is it a VHDL or a Verilog design? > and number of clk? Answer this question first: how many clocks do you need at all? If you don't know an answer, then the correct answer may be: ONE!
my design written in VHDL code i need one clock for all design how can archive this?
> i need one clock for all design how can archive this? Usually this is the clock from a xtal-oscillator in the range of 30..100MHz. And these descritpion result in a clocked flipflop in a VHDL design:
if clk50MHz'event and clk50MHz='1' then
if rising_edge(clk50MHz) then
if falling_edge(clk50MHz) then
wait until clk50MHz'event and clk50MHz='1';
wait until rising_edge(clk50MHz);
wait until falling_edge(clk50MHz);
So whereever a similar construct appears, there must be used the same signal. Then you have only one clock source over the whole FPGA.
i use if(clk'event and clk='1') then ------------- ------------- end if; for 18 times but the BUFGMUX is 18 from 24 why??
> for 18 times > but the BUFGMUX is 18 from 24 why?? Is clk always the same signal? Duke
yes is same signal for all design
Can you show us an example of your code? Duke