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Subject Author Replies Last post
ARM pessimizer Paul DeRocco 4
for loop generate find a good syntax. Olivier D. 0
Old diskets to be used as rotary encoder Christian 6
ps2 interface with fpga ahmed 3
Hot FPGA REASONS Rashmi Imhsar 1
error: * can not have such operands in this context Mariem Makni 1
State Machines for an equation Hassan Mahmood 0
rhl 401 relay replacement or substitute Sam Telford 0
solution for large memory requirement for FPGA Vinayak S. 1
quick response: please help me to clear the warnings Padma Baskaran 20
use the output from counter basma hassan 11
How to include deadtime in pwm generator Tosin Akin 6
time duration for every key in keyboard ahmedhassan 9
Verilog module Need help designing a circuit 4
division on the last outputs Basma Hassan 7
Microblaze documentation Abdallah      0
design works on fpga, but in simulation a counter is always 'x' Jay Christnach 3
query on verilog code pushpalatha Gowda 4
Raspberry Pi PIR motion sensor power supply with Schmitt Trigger Axel Meyer 0
locked Call for mentors and students for Google Summer of Code 2014! Google awards stipends of US$5500 Andreas Hornig 0
custom processor on FPGA Lovish Jain 1
writting code in vhdl basma 9
online receive bmp tp fpga Abdallah      6
Monokai color theme for em::blocks? Holla 2
How to use Memory Abdallah      3
Pre-synthesis and post-synthesis Simulation not matched! Nisarg Shah 29
read data from file Abdallah      6
problem in vhdl code agathepower 9
Problem with atmega -8 Ajay R. 16
How to increases Maximum operating freqency Vinayak S. 3
Atmel Studio: how to change compiler output directory? Markus Grabner 1
GTP Transciever Alexander Lutovid 3
check lsb in vhdl basma 1
sorter in vhdl basma 1
communication between two ATmega32 via TWI/I2C interface Va Ma 5
Error in Post-synthesis, ModelSim Vinayak S. 1
Tools required for testing and debugging AVB Sridhar 1
regulated transformer in LTSpice Andreas Gruber 5
16x2 lcd help Ajay R. 7
Use Counting Tube as VU-Meter Dr. Dentz. 0
vhdl code to find max value from input basma 10
Need help with reading from file Miller Jackson 3
Yagarto BUG: static vars are offset in memory by 4 bytes. David Lee 9
how to implement interleaver in FPGA Vinayak S. 8
Debugging cortex-m3 in GDB with J-Link causes SIGTRAPs Artem Pisarenko 2
dividing clock Bilel 13
state machine in vhdl Basma Hassan 20
how to solve this linker script error? Hemanth Venkatappa 6
Single Entity - Multiple architectures SM 1
Not synthesizing Vinayak S. 21
Signal Process Frhling M. 0