Forum: FPGA, VHDL & Verilog RCA Testbench returns XXXXXXXX for 32 bit adder


von Hakim M. (Company: student) (feiyim)


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I dont know why my testbench is returning unknowns for subtraction in 
the ALU RCA. Am trying to do B XOR Cin to perform subtraction according 
to the diagram:

https://www.electronicshub.org/wp-content/uploads/2015/06/Parallel-subtactor-and-adder.jpg

von Lothar M. (lkmiller) (Moderator)


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Hakim M. wrote:
> my testbench
Pls attach your vhdl files as vhdl files instead of pictures. Because 
then its easy to search the code and check out the problem for 
oneself...

: Edited by Moderator
von -gb- (Guest)


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Well, there are many errors.

temp_b is a std_logic, but you drive it parallel with 32 signals which 
results in a conflict indicated by X in simulation.

Component FA is not included in your post.

overflow and carry outputs will only pulse for a very short time.

Too complicated testbench. This should be done much simpler, i attached 
gb_arith_tb.vhd as an example.

But the circuit in the linked image simulates fine.

von -gb- (Guest)


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But it is almost correct. It works if you declare temp_b inside the 
generate block.

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