Well, there are many errors.

temp_b is a std_logic, but you drive it parallel with 32 signals which 
results in a conflict indicated by X in simulation.

Component FA is not included in your post.

overflow and carry outputs will only pulse for a very short time.

Too complicated testbench. This should be done much simpler, i attached 
gb_arith_tb.vhd as an example.

But the circuit in the linked image simulates fine.

But it is almost correct. It works if you declare temp_b inside the 
generate block.