library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Arith_tb is
end Arith_tb;

architecture sim of Arith_tb is

component Arith is
	port(
		A        : in  std_logic_vector(31 downto 0);
		B        : in  std_logic_vector(31 downto 0);
		Cin      : in  std_logic;
		result   : out std_logic_vector(31 downto 0);
		overflow : out std_logic;
		carry    : out std_logic
	);
end component;

signal A        : std_logic_vector(31 downto 0);
signal B        : std_logic_vector(31 downto 0);
signal result   : std_logic_vector(31 downto 0);
signal op       : std_logic_vector(3 downto 0);
signal temp     : std_logic_vector(31 downto 0);
signal overflow : std_logic;
signal cin      : std_logic;
signal carry    : std_logic;

type test_vector is record
	A_tv      : std_logic_vector(31 downto 0);
	B_tv      : std_logic_vector(31 downto 0);
	result_tv : std_logic_vector(31 downto 0);
	op_tv     : std_logic_vector(3 downto 0);
end record;

type test_vector_array is array(natural range<>) of test_vector;

constant test_vectors : test_vector_array := (
	(x"00000000", x"00000000", x"00000000", "0000"),
	(x"00000001", x"00000001", x"00000000", "0010"),
	(x"00000002", x"00000001", x"00000001", "0010")
);

begin

inst_Arith : Arith
	port map(
		A        => A,
		B        => B,
		Cin      => Cin,
		result   => result,
		overflow => overflow,
		carry    => carry
	);

process begin
	for i in test_vectors'range loop
		A   <= test_vectors(i).A_tv;
		cin <= test_vectors(i).op_tv(1);
		B   <= test_vectors(i).B_tv;
		wait for 1 ns;
		result <= temp;
		assert (temp = test_vectors(i).result_tv)
		report "----Failure at test_vector("
			& integer'image(i) & ")."
			& " Expected value is " & to_hstring(test_vectors(i).result_tv)
			& ". Result(temp) was " & to_hstring(temp)
			& " For values A = " & to_hstring(test_vectors(i).A_tv)
			& ", B = " & to_hstring(test_vectors(i).B_tv)
			& " opCode = " & to_hstring(test_vectors(i).op_tv)
			& " : V = " & std_logic'image(overflow)
			& " , Cout = " & std_logic'image(carry)
			& " , Cin " & std_logic'image(cin)
		severity note;
		wait for 10 ns;
	end loop;
	wait;
end process;

end;