library ieee;
use ieee.std_logic_1164.all;

entity FA is
	port(
		A    : in  std_logic;
		B    : in  std_logic;
		Cin  : in  std_logic;
		Sum  : out std_logic;
		Cout : out std_logic
	);
end FA;

architecture rtl of FA is

begin

Sum  <= A xor B xor Cin;
Cout <= ((A xor B) and Cin) or (A and B);

end;