library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Arith is
	port(
		A        : in  std_logic_vector(31 downto 0);
		B        : in  std_logic_vector(31 downto 0);
		Cin      : in  std_logic;
		result   : out std_logic_vector(31 downto 0);
		overflow : out std_logic;
		carry    : out std_logic
	);
end Arith;

architecture rtl of Arith is

component FA is
	port(
		A    : in  std_logic;
		B    : in  std_logic;
		Cin  : in  std_logic;
		Sum  : out std_logic;
		Cout : out std_logic
	);
end component;

signal C      : std_logic_vector(32 downto 0);
signal temp_b : std_logic;

begin

C(0) <= Cin;

Gen_FA : for i in 1 to 32 generate
	temp_b <= B(i - 1) xor Cin;
	cell_i : FA
		port map(
			A    => A(i - 1),
			B    => temp_b,
			Cin  => C(i - 1),
			Sum  => result(i - 1),
			Cout => C(i)
		);
end generate;

carry    <= C(32);
overflow <= C(32) xor C(31);

end;