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-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:56:57 01/08/2018 
-- Design Name: 
-- Module Name:    x7seg_top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity x7seg_top is
		port (
			clk: in std_logic;
			Anode_Active: out std_logic_vector (3 downto 0);
			LED: out std_logic_vector (6 downto 0));
end x7seg_top;

architecture Behavioral of x7seg_top is

signal clk_out,clk_out2: std_logic;

begin

	clock_second: entity work.freqDivGen generic map(100_000_000) port map (clk, clk_out);
	clock: entity work.freqDivGen generic map (500_000) port map(clk, clk_out2);
	DEDA: entity work.x7seg port map (clk_out2,clk_out, Anode_Active, LED);
	
	

end Behavioral;