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-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:15:14 01/08/2018 
-- Design Name: 
-- Module Name:    x7seg - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity x7seg is
	port (
			clk_out,clk_out2: in std_logic;
			Anode_Active: out std_logic_vector (3 downto 0);
			LED: out std_logic_vector (6 downto 0));
end x7seg;

architecture Behavioral of x7seg is

signal led_activating: std_logic_vector (1 downto 0);

signal show: std_logic_vector (3 downto 0);

begin

		process (clk_out)
			begin
				if (clk_out'EVENT and clk_out='1') then
					if (led_activating = "11") then
						led_activating <= "00";
					end if;
					led_activating <= led_activating+1;
				end if;
		end process;	
	
	process(led_activating)
	begin
						case led_activating is
						when "00" => Anode_Active <= "0111";
										 LED <= "0100001"; --d
						when "01" => Anode_Active <= "1011";
										 LED <= "0000110"; --E
						when "10" => Anode_Active <= "1101";
								  LED <= "0100001"; --d
						when others => Anode_Active <= "1110";
								  LED <= "0001000"; --A
					end case;
	end process;
		
	
	process(clk_out2)
	begin
		if (clk_out2'EVENT and clk_out2='1') then
			case clk_out2 is
				when '1' => show <= "0000";
			
				when others => show <= "1111";
			end case;

		end if;
		end process;

end Behavioral;