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-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:13:24 01/08/2018 
-- Design Name: 
-- Module Name:    freqDivGen - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity freqDivGen is
	generic (nfCLK: natural :=100);
	port(
		clk: in std_logic:='0';
		clk_o: buffer std_logic:='0');
end freqDivGen;

architecture Behavioral of freqDivGen is

begin
	process (clk)
	variable temp: integer range 0 to nfCLK/2:=0;
	begin
		if (clk'EVENT and clk='1') then
			temp:=temp+1;
			if (temp>=nfCLK/2) then
				clk_o<=not clk_o;
				temp:=0;
			end if;
		end if;
end process;

end Behavioral;